NIS4461 [ONSEMI]
9 to 24 Volt Electronic Fuse;
| 型号： | NIS4461 |
| 厂家： | 
ONSEMI |
| 描述： | 9 to 24 Volt Electronic Fuse |
| 文件： | 总12页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9 to 24 Volt Electronic Fuse
NIS4461 Series
The NIS4461 eFuse is a cost effective, resettable fuse which can
greatly enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to protect the downstream circuitry against an
overcurrent event by limiting the current while protecting against high
inrush current, as well as monitoring the load current in real time.
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Features
4.2 AMP, 9 to 24 VOLT
ELECTRONIC FUSE
• Integrated Power Device
• Power Device Thermally Protected
• No External Current Shunt Required
• 9 V to 24 V Input Range
• 39 mW Typical
MARKING
DIAGRAM
• Internal Charge Pump
XXXXX
XXXXX
ALYWG
G
• Internal Undervoltage Lockout Circuit
WDFN10
CASE 522AA
• ESD Ratings:
Human Body Model (HBM); 2000 V
Charged Device Model (CDM); 2000 V
Latch−Up; Class 1
XXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Y
W
G
= Year
= Work Week
= Pb−Free Package
Compliant
Typical Applications
• Hard Drives
• Mother Board Power Management
• Fan Drives
• Industrial
• Handheld Devices
• Portable Instruments
(Note: Microdot may be in either location)
PIN CONNECTIONS
Src
Src
Src
Src
Src
GND
dV/dt
En/Flt
V
CC
I
LIM
SENSE
NC/I
WDFN10
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
ordering information section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
March, 2021 − Rev. 2
NIS4461/D
NIS4461 Series
VCC
Charge
Pump
Enable
ENABLE/
FAULT
SOURCE
Current
Limit
Thermal
Shutdown
I
LIMIT
UVLO
dv/dt
dv/dt
Control
GND
Figure 1. Block Diagram
(NIS4461MT2TXG, NIS4461MT4TXG)
VCC
Charge
Pump
Enable
ENABLE/
FAULT
SOURCE
Current
Limit
Thermal
Shutdown
I
I
LIMIT
Current
Monitor
SENSE
UVLO
dv/dt
dv/dt
Control
Voltage
Clamp
GND
Figure 2. Block Diagram
(NIS4461MT1TXG, NIS4461MT3TXG
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2
NIS4461 Series
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
1
Function
Ground
dv/dt
Description
Negative input voltage to the device. This is used as the internal reference for the IC.
2
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal
capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this
pin to increase the ramp time. If an additional time delay is not required, this pin should be left open.
3
Enable/Fault
The enable/fault pin is a tri−state, bidirectional interface. It can be pulled to ground with external
open−drain or open collector device to shutdown the eFuse. It can also be used as a status indicator;
if the voltage level is intermediate around 1.4 V − the eFuse is in the thermal shutdown, if the voltage
level is high around 3 V − the eFuse is operating normally. Do not actively drive this pin to any
voltage. Do not connect a capacitor to this pin.
4
5
I
A resistor between this pin and the source pin sets the overload and short circuit current limit levels.
For NIS4461MT2TXG and NIS4461MT4TXG
Limit
NC
I
For NIS4461MT1TXG and NIS4461MT3TXG load current monitor allows the system to monitor the
SENSE
load current in real time. Connect R
to GND.
SENSE
6−10
Source
This pin is the source of the internal power FET and the output terminal of the fuse. Connect an
electrolytic capacitor or Schottky diode for 27 V or higher.
11 (belly pad)
V
CC
Positive input voltage to the device.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (V to GND, Note 1)
V
IN
−0.6 to 30
−0.6 to 30
V
CC
Transient (100 ms)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
Table 2. THERMAL RATINGS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Air
q
90
°C/W
JA
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Lead
Y
27.5
27.5
7.6
°C/W
°C/W
°C/W
J−L
J−B
J−T
max
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Board
Y
Y
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Case Top
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Total Power Dissipation @ T = 25°C
P
1.39
11.1
W
mW/°C
A
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Derate above 25°C
Operating Ambient Temperature Range
Operating Junction Temperature Range
Non−operating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
−40 to 125
−40 to 150
−55 to 155
260
°C
°C
°C
°C
A
T
J
T
STG
T
L
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3
NIS4461 Series
ELECTRICAL CHARACTERISTICS (V = 24 V, C = 100 mF, dv/dt pin open, R
= 20 W, T = 25°C unless otherwise noted.)
j
CC
L
LIMIT
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
Delay Time (enabling of chip to I = 100 mA with 1 A resistive load)
T
dly
−
220
−
ms
D
Kelvin ON Resistance (Note 2)
J
R
30
−
39
60
50
−
mW
DSon
T = 140°C (Note 3)
2
Continuous Current (T = 25°C, 0.5 in copper) (Note 3)
A
I
D
I
D
−
−
4.2
2.5
−
−
A
A
(T = 80°C, minimum copper)
THERMAL LATCH
Shutdown Temperature (Note 3)
Thermal Hysteresis (Auto−retry part only)
Thermal Shutdown Response Time
UNDERVOLTAGE PROTECTION
Undervoltage Lockout
T
150
−
175
45
200
−
°C
°C
ms
SD
T
Hyst
T
SD
10
15
20
Res
V
UVLO
6
6.5
7
V
V
UVLO Hysteresis
V
Hyst
−
0.80
−
CURRENT LIMIT
Kelvin Short Circuit Current Limit (R
= 20 W, Note 4)
I
1.76
2.1
4.6
2.64
A
A
Limit
Lim−SS
Kelvin Overload Current Limit (R
= 20 W, Note 4)
I
−
−
Limit
Lim−OL
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to V
Output Voltage Ramp Time
= 23.7 V)
t
t
−
−
2.0
1.2
−
−
ms
ms
OUT
slew
slew
(10% to 90% − V
= 2.4 V to 21.6 V with 24W Load)
OUT
Maximum Capacitor Voltage
V
max
−
−
V
CC
V
ENABLE/FAULT
Logic Level Low (Output Disabled)
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled)
High State Maximum Voltage
V
0.35
0.82
1.96
2.51
−
0.58
1.4
2.6
4.6
−15
−
0.81
1.95
3.0
5
V
V
in−low
in−mid
in−high
in−max
in−low
V
V
V
V
V
Logic Low Sink Current (V
= 0 V)
I
−25
1.0
3.0
mA
mA
Units
enable
Logic High Leakage Current for External Switch (V
= 3.3 V)
I
−
enable
in−leak
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
Fan
−
−
TOTAL DEVICE
Bias Current (Operational)
Bias Current (Shutdown)
LOAD CURRENT MONITOR
I
I
−
−
−
−
450
220
mA
mA
Bias
Bias
Current Monitor Sense (R
= 1 kW)
I
−
1
−
mA/A
%
SENSE
SENSE
Current Monitor Sense Accuracy
I
−10
−
10
ACC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse test: Pulse width 300 ms, duty cycle 2%.
3. Verified by design.
4. Refer to explanation of short circuit and overload conditions in application note AND9441.
5. Device will shut down prior to reaching this level based on actual UVLO trip point.
6. For output slew rate calculation with external capacitor, please refer to ”Output Slew Rate (dv/dt)” in the ”Application Information ” section
www.onsemi.com
4
NIS4461 Series
100
−40_C
25_C
10
85_C
1
0
10
20
30
40
50
60
70
80
POWER (W)
Figure 3. Thermal Trip Time vs. Power Dissipation
11
10
9
V
CC
+12 V
8
7
6
SOURCE
NIS4461MT2/4
R
S
4
I
LIMIT
3
ENABLE/
FAULT
GND
dv/dt
2
LOAD
1
ENABLE
GND
Figure 4. Application Circuit with Direct Current Sensing
11
10
9
8
+12 V
V
CC
SOURCE
7
6
NIS4461MT1/3
R
S
4
I
LIMIT
3
ENABLE
GND
I
SENSE
R
SENSE
dv/dt
2
LOAD
1
ENABLE
GND
Figure 5. Application Circuit with Direct Current Sensing
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5
NIS4461 Series
V
CC
V
CC
SOURCE
SOURCE
R
S
NIS5420
NIS4461
I
LIMIT
I
LIMIT
ENABLE/
FAULT
ENABLE/
FAULT
dv/dt
dv/dt
GND
GND
LOAD
LOAD
ENABLE
Figure 6. Common Thermal Shutdown
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6
NIS4461 Series
TYPICAL CHARACTERISTICS
2.0
1.95
1.9
4.5
4
3.5
3
1.85
1.8
2.5
2
1.75
1.7
1.5
1
1.65
1.6
0.5
0
1.55
1.5
−40
−20
0
20
40
60
80
100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
TEMPERATURE (°C)
LOAD CURRENT (A)
Figure 7. VISENSE vs. Temperature
Figure 8. VISENSE vs. Load Current
50
48
46
44
42
40
38
36
34
32
30
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
(V)
20
25
30
−40
−20
0
20
40
60
80
100
V
TEMPERATURE (°C)
CC
Figure 9. RDS(ON) vs. VCC
Figure 10. RDS(ON) vs. Temperature
10
9
8
7
6
5
4
3
2
1
0
8
I
, R
= 10 W
= 10 W
OL
LIM
7
6
5
4
3
2
1
0
I
, R
LIM
SC
I
OL
I
, R
= 20 W
OL
LIM
I
, R
, R
= 40 W
OL
LIM
I
SC
I
, R
= 20 W
SC
LIM
I
= 40 W
SC
LIM
−40
−20
0
20
40
60
80
100
0
10
20
30
40
(W)
50
60
70
TEMPERATURE (°C)
R
LIM
Figure 11. IOL and ISC vs. Temperature
Figure 12. IOL and ISC vs. RLIM
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7
NIS4461 Series
TYPICAL CHARACTERISTICS
30
V
CC
= 24 V
I
= 1 A
LOAD
25
20
15
10
5
0
0
100
200
300
400
500
600
Capacitance from dV/dt Pin to GND (pF)
Figure 13. Slew Rate Control Screenshot
Figure 14. TSLEW vs. dV/dt Capacitance
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. TSLEW vs. Temperature
Figure 16. UVLO TURN ON vs. Temperature
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8
NIS4461 Series
APPLICATION INFORMATION
Basic Operation
to the direct sense method since only four of the source pins
are used for power.
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The dv/dt of the output voltage will be
controlled by the internal dv/dt circuit. The output voltage
will slew from 0 V to the rated output voltage in 1 ms, unless
additional capacitance is added to the dv/dt pin.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The current limit circuit does not shut down the part but will
reduce the conductivity of the FET to maintain a constant
current at the internally set current limit level.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
Undervoltage Lockout
The undervoltage lockout circuit uses a comparator with
hysteresis to monitor the input voltage. If the input voltage
drops below the specified level, the output switch will be
switched to a high impedance state.
Output Slew Rate dv/dt
The dv/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor.
The default ramp time is approximately 1 ms. This can be
modified by adding an external capacitor at the dv/dt pin.
This pin includes an internal current source of
approximately 85 nA. Since the current level is very low, it
is important to use a ceramic cap or other low leakage
capacitor. Aluminum electrolytic capacitors are not
recommended for this circuit.
between the input voltage (V ) and ground.
CC
Current Limit
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor as well as increasing
the value and decreasing the power rating of the sense
resistor. Sense resistors are typically in the tens of ohms
range with power ratings of several milliwatts making them
very inexpensive chip resistors.
The current limit circuit has two limiting values, one for
short circuit events which are defined as the mode of
operation in which the gate is high and the FET is fully
enhanced. The overload mode of operation occurs when the
device is actively limiting the current and the gate is at an
intermediate level. For a more detailed description of this
circuit please refer to application note AND9441.
The ramp time from 0 to the nominal output voltage can
be determined by the following equation, where t is in
seconds:
ǒ
Ǔ
t2.4*21.6 + 3.8e7 @ 28 pF ) Cext ) 0.00127
ǒ
Ǔ
t
2.4−21.6 * 0.00127
Cext
+
* 28 pF
3.8e7
Where:
C is in Farads
t is in seconds
Any time that the unit shuts down due to a fault, enable
shut−down, or recycling of input power, the timing capacitor
will be discharged and the output voltage will ramp from 0
at turn on.
There are two methods of biasing the current limit circuit
for this device. They are shown in the two application
figures. Direct current sensing connects the sense resistor
between the current limit pin and the load. This method
includes the bond wire resistance in the current limit circuit.
This resistance has an impact on the current limit levels for
a given resistor and may vary slightly depending on the
impedance between the sense resistor and the source pins.
The on resistance of the device will be slightly lower in this
configuration since all five source pins are connected in
parallel and therefore, the effective bond wire resistance is
one fifth of the resistance for any given pin.
The other method is Kelvin sensing. This method uses one
of the source pins as the connection for the current sense
resistor. This connection senses the voltage on the die and
therefore any bond wire resistance and external impedance
on the board have no effect on the current limit levels. In this
configuration the on resistance is slightly increased relative
Enable/Fault
The Enable/Fault pin is a multi−function, bidirectional pin
that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit.
To use as a simple enable pin, an open drain or open
collector device should be connected to this pin. Due to its
tri−state operation, it should not be connected to any type of
logic with an internal pullup device.
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family,
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9
NIS4461 Series
a thermal shutdown of one device will cause both devices to
disable their outputs. Both devices will turn on once the fault
is removed for the auto−retry devices.
For the latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
an external switch and then allowed to go high or after the
input power has been recycled. For the auto retry devices,
both devices will restart as soon as the die temperature of the
device in shutdown has been reduced to the lower thermal
limit.
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. Output power can
be restored by either recycling the input power or toggling
the enable pin for thermally latching devices. Power will
automatically be reapplied to the load for auto−retry devices
once the die temperature has been reduced by 45°C.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
Thermal Protection
The NIS4461 includes an internal temperature sensing
circuit that senses the temperature on the die of the power
3.3 V
1.95 V
0.81 V
Gnd
Figure 17. Fault/Enable Signal Levels
Startup
Blanking
12 mA
Enable SD
2.64 V
0.58 V
+
−
Enable/Fault
1.4 V
−
+
Thermal Reset
SD
Thermal
Shutdown
Thermal SD
Figure 18. Enable/Fault Simplified Circuit
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10
NIS4461 Series
ORDERING INFORMATION
†
Device
Marking
Features
ISENSE
Yes
Package
Shipping
NIS4461MT1TXG
NIS4461MT2TXG
NIS4461MT3TXG
NIS4461MT4TXG
61T1
61T2
61T3
61T4
Thermal Latching
Thermal Latching
Auto−Retry
No
WDFN10
(Pb−Free)
3000 / Tape & Reel
Yes
Auto−Retry
No
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NIS4461 Series
PACKAGE DIMENSIONS
WDFN10, 3x3, 0.5P
CASE 522AA
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
B
E
A
MILLIMETERS
PIN ONE
REFERENCE
DIM
A
MIN
0.70
0.00
NOM
0.75
MAX
0.80
0.05
A1
A3
b
0.03
0.20 REF
0.24
2X
0.15 C
0.18
2.45
1.75
0.30
2.55
1.85
D
3.00 BSC
2.50
2X
0.15
C
D2
E
TOP VIEW
3.00 BSC
1.80
A3
E2
e
0.50 BSC
0.19 TYP
0.40
0.10
0.08
C
K
A
L
0.35
0.45
10X
C
A1
SEATING
C
SIDE VIEW
D2
PLANE
SOLDERING FOOTPRINT*
2.6016
10X
L
e
1
5
E2
1.8508 3.3048
2.1746
10X
K
10
6
b 10X
10X
0.10
0.05
C
C
A
B
0.5651
10X
NOTE 3
BOTTOM VIEW
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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