NIS5021MT2TXG [ONSEMI]
12 Volt Electronic Fuse;
| 型号： | NIS5021MT2TXG |
| 厂家： | 
ONSEMI |
| 描述： | 12 Volt Electronic Fuse |
| 文件： | 总14页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NIS5020, NIS5021, NIS5820
+12 Volt Electronic Fuse
The NIS5x2x Series eFuse is a cost effective, resettable fuse which
can greatly enhance the reliability of a hard drive or other circuit from
both catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits. It includes an overvoltage clamp
circuit that limits the output voltage during transients but does not shut
the unit down, thereby allowing the load circuit to continue its
operation.
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Features
• 14 mW and 24 mW Typical R
• Tristate Enable
Options
DS(on)
1
WDFN10 4x4
CASE 511DS
WDFN10 3x3
CASE 522AA
• Overcurrent Protection
• Thermally Protected
• Integrated Soft−Start Circuit
MARKING DIAGRAM
• Fast Response Overvoltage Clamp Circuit
• Internal Undervoltage Lockout Circuit
• Internal Charge Pump
XXXXXX
XXXXXX
ALYWG
G
• NIS5020 and NIS5820 in WDFN10 3x3
• NIS5021 in WDFN10 4x4
XXXX = Specific Device Code
• Hot Pluggable
= (See ORDERING INFORMATION
= table below)
= Assembly Location
= Wafer Lot
• ESD HBM Rating: 1.5 kV
A
L
Y
W
G
• ESD CDM Rating: 1.0 kV
= Year
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
= Work Week
= Pb−Free Package
Compliant
Typical Applications
• Hard Drives
(Note: Microdot may be in either location)
• Solid State Drives
• Servers
PIN CONNECTIONS
1
• Mother Boards
• Fan Drives
Source
Source
Source
Source
Source
GND
dV/dt
Enable/Fault
V
CC
I
LIMIT
NC
WDFN10
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2019 − Rev. 3
NIS5020/D
NIS5020, NIS5021, NIS5820
Vcc
Charge
Pump
Enable/Fault
Enable/Fault
Source
Current
Limit
I
LIMIT
Thermal
Shutdown
Voltage
Clamp
dv/dt
Control
dV/dt
UVLO
GND
Figure 1. Block Diagram
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2
NIS5020, NIS5021, NIS5820
Figure 2. Application Circuit with Kelvin Current Sensing
NIS5135
Figure 3. Common Thermal Shutdown between 12 V and 5 V Family Devices
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3
NIS5020, NIS5021, NIS5820
Figure 4. Application Circuit with Direct Current Sensing
Figure 5. Paralleling eFuses
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4
NIS5020, NIS5021, NIS5820
PIN FUNCTION DESCRIPTION
Pin No.
DFN10
Pin Name
Description
1
2
GND
Negative input voltage to the device. This is used as the internal reference for the IC.
dV/dt
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that
allows it to ramp up over a period of 1 ms. An external capacitor can be added to this pin to increase the ramp
time. If an additional time delay is not required, this pin should be left open.
3
Enable/
Fault
The enable/fault pin is a tri−state, bidirectional interface. It can be pulled to ground with an external open−drain
or open collector device to shut down the eFuse. It can also be used as a status indicator; if the voltage level is
intermediate (around 1.4V), the eFuse is in thermal shutdown. If the voltage level is high (around 3V) the eFuse
is operating normally. Do not actively drive this pin to any voltage. Do not connect a capacitor to this pin.
4
5
I
A resistor between this pin and the source pin sets the overload and short circuit current limit levels
No Connect. Leave this pin unconnected.
LIMIT
NC
6−10
Source
Source of the internal power FET and the output terminal of the fuse
11
(Pad)
V
CC
Positive input voltage to the device. Connect a 1.0 mF or greater capacitor from V to GND as close as possi-
CC
ble to the IC.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (VCC to GND)
V
CC
−0.3 to +18
−0.3 to +20
V
Transient (100 ms) (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Guaranteed by characterization only.
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5
NIS5020, NIS5021, NIS5820
THERMAL RATINGS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Air, NIS5020
q
°C/W
JA
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Resistance, Junction−to−Air, NIS5021
50
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
40
Thermal Characterization Parameter, Junction−to−Top
Y
Y
2.6
°C/W
°C/W
J−T
J−B
max
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Board
11.7
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Total Continuous Power Dissipation, NIS5020 @ T = 25°C
P
A
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
2.5
20
W
mW/°C
Derate above 25°C
Total Continuous Power Dissipation, NIS5021 @ T = 25°C
P
max
A
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
3.1
25
W
mW/°C
Derate above 25°C
Operating Temperature Range
Non−operating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
T
−40 to 150
−55 to 150
260
°C
°C
°C
J
J
L
T
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V = 12 V, C = 20 mF, dV/dt pin open, R
= 75 W, T = 25°C)
CC
L
LIM
A
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
Delay Time (enabling of chip to V
0 mF)
rising to 10% of V = 12 V, C
=
T
DLY
200
ms
OUT
CC
OUT
ON Resistance (Note 4)
NIS5020
NIS5021
NIS5820
NIS5020
NIS5021
NIS5820
NIS5020
NIS5021
NIS5820
NIS5020
NIS5021
NIS5820
NIS5021
R
11
11
19
14
14
24
22
22
37
6.6
6.9
5.0
10
11
18
18
30
mW
DSON
ON Resistance
R
mW
A
DSON@140C
T = 140°C (Note 5)
J
Continuous Current
I
D
I
D
I
D
2
(T = 25°C), 100 mm 1 oz. Cu per layer, one layer
A
(Note 5)
Continuous Current
A
(T = 25°C), 4 layer PCB High−K JEDEC JESD51−7,
A
2
>800 mm , 2 oz. Cu (Note 5)
8.0
12
Continuous Current
A
(T = 25°C), 12 layer PCB, 2 oz. Cu,
A
2
15000 mm (per layer)
Off State Leakage (V = 12 V, EN = 0)
I
1
mA
in
OFF
THERMAL LATCH
Shutdown Temperature (Notes 2, 5)
T
150
175
45
200
°C
°C
SD
Thermal Hysteresis (Decrease in die temperature for turn on, does not apply to
latching parts)
T
HYST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. eFuse is latched off until the En/Fault pin is pulled low and then released or a power on reset is applied to the device.
3. Does not include fan out of Enable/Fault function.
4. Pulse test: Pulse width 300 s, duty cycle 2%
5. Verified by design.
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6
NIS5020, NIS5021, NIS5820
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V = 12 V, C = 20 mF, dV/dt pin open, R
= 75 W, T = 25°C)
A
CC
L
LIM
Characteristics
UNDER/OVERVOLTAGE PROTECTION
Maximum (V = 18 V)
Symbol
Min
Typ
Max
Unit
V
OUT
V
out−clamp
13
14
15
V
V
V
CC
Undervoltage Lockout (Turn on, Voltage Going High)
UVLO Hysteresis
V
UVLO
7.8
8.5
0.8
9.2
V
Hyst
KELVIN CURRENT LIMIT
NIS5020/
NIS5021
I
7.6
3.4
5.3
2.0
A
A
A
A
Overload/Trip Current, Rlim = 75 W
Short Circuit/Holding Current Rlim = 75 W
Overload/Trip Current, Rlim = 75 W
Short Circuit/Holding Current Rlim = 75 W
SLEW RATE CONTROL
TRIP
I
I
1.8
1.3
0.7
5.0
2.7
1.9
HOLD
NIS5820
I
TRIP
HOLD
Slew Rate (no capacitor on dV/dt pin)
ENABLE/FAULT
SR
1.0
ms
Logic Level Low (Output Disabled)
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled)
High State Maximum Voltage
V
0.35
0.82
1.96
2.51
0.58
1.4
0.81
1.95
2.5
V
V
in−low
in−mid
in−high
in−max
in−low
V
V
V
2.2
V
3.3
5.0
V
Logic Low Sink Current (V
= 0 V)
I
−17
−25
1.0
mA
mA
Units
ENABLE
Logic High Leakage Current for External Switch (V
= 3.3 V)
I
in−leak
ENABLE
Maximum Fanout for Fault Signal (Total number of chips that can be connect-
ed to this pin for simultaneous shutdown)
Fan
3.0
TOTAL DEVICE
Bias Current
I
650
800
mA
Bias
Operational (I
= 0 A)
Load
Shutdown (EN = 0) (Note 3)
Fault
100
110
150
200
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. eFuse is latched off until the En/Fault pin is pulled low and then released or a power on reset is applied to the device.
3. Does not include fan out of Enable/Fault function.
4. Pulse test: Pulse width 300 s, duty cycle 2%
5. Verified by design.
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7
NIS5020, NIS5021, NIS5820
TYPICAL CHARACTERISTICS
14
12
10
8
20
Overload/Trip
18
16
Thermal Shutdown
14
12
10
Short Circuit/Hold
Trip/OL
6
8
6
4
4
2
0
Hold/SC
2
0
−2
0
0.002
0.004
0.006
0.008
0.010
0.012
20
30
40
50
60
(W)
70
80
90 100
TIME (ms)
R
LIMIT
Figure 6. Slow Fault Current Limit
Characteristic of NIS5020
Figure 7. NIS5020/NIS5021 Current Limit vs.
LIMIT for Kelvin Sensing
R
12
10
8
26
24
22
20
18
16
14
12
10
8
Trip/OL
6
4
Hold/SC
6
2
4
2
0
0
0
5
10 15
20 25 30 35 40 45 50
20
30
40
50
60
70
80
90 100
R
(W)
CAPACITANCE (nF)
LIMIT
Figure 8. NIS5820 Current Limit vs. RLIMIT for
Kelvin Sensing
Figure 9. Output Voltage Ramp Time vs. dv/dt
Capacitance
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8
NIS5020, NIS5021, NIS5820
TYPICAL CHARACTERISTICS
Figure 10. NIS5020 Slew Rate Control
Figure 11. NIS5020 Overvoltage Clamp
Operation
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9
NIS5020, NIS5021, NIS5820
APPLICATIONS INFORMATION
Paralleling eFuses
operation in which the gate is high and the FET is fully
enhanced. The overload mode of operation occurs when the
device is actively limiting the current and the gate is at an
intermediate level. For a more detailed description of this
circuit please refer to application note AND9441.
If the output current capability required by an application
is higher than the current which can be carried by a single
eFuse, it is possible to parallel eFuses to achieve a higher
current throughput. Up to four eFuses can be paralleled to
achieve a higher current. All of the eFuses will have a
common thermal shutdown. Refer to Figure 5 for the
schematic connection of parallel eFuses. The VCC pins of
every eFuse must be shorted together. The Source pins of
each eFuse must be shorted together. Each eFuse should be
configured either in Kelvin or Direct mode and have its
individual current limiting resistor Rlim connected between
Connection of R
current limit setting resistor can be
LIMIT
made as shown in Figure 2 (Kelvin connection), or Figure 4
(Direct connection). Both connections result in a similar
current limit thresholds and behavior. It is important to make
sure that layout trace connecting R
resistor to pins 4
LIMIT
and 6 is as short as possible. The shortest possible distance
on a PCB must be used to connect pin 6 to R resistor
LIM
I
and Source pins. The Enable pins of all the eFuses
before pin 6 is connected to a common load node.
LIMIT
must be shorted together for common shutdown
functionality and connected to an open−drain or open
collector device in case it is desired to turn off all the eFuses
at the same time. The dv/dt pins of eFuses must NOT be
shorted together; they should be either left floating for a
standard output ramp−up time or have individual dvdt
capacitor to ground.
Every eFuse will carry equal amount of current during
normal operation and overcurrent events. If any of the
eFuses goes to thermal shutdown first, it will pull down the
Enable pin and make the other eFuses to shut down as well.
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
voltage exceeds 14 V, the gate drive of the main FET is
reduced to limit the output. This is intended to allow
operation through transients while protecting the load. If an
overvoltage condition exists for many seconds, the device
may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device. Refer to
Figure 12 for typical overvoltage clamp behavior
Basic Operation
Undervoltage Lockout
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The output voltage, which is controlled
by an internal dV/dt circuit, will slew from 0 V to the rated
output voltage in 1 ms. The device will remain on as long as
the temperature does not exceed the 175°C limit that is
programmed into the chip.
The internal current limit circuit does not shut down the
part but will reduce the conductivity of the FET to maintain
a constant current at the internally set current limit level. The
input overvoltage clamp also does not shutdown the part, but
will limit the output voltage in the event that the input
exceeds the Vclamp level.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
The undervoltage lockout circuit uses a comparator with
hysteresis to monitor the input voltage. If the input voltage
drops below the specified level, the output switch will be
switched to a high impedance state.
Slew Rate Control
The dV/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor.
The default ramp time is approximately 1 ms. This pin
includes an internal current source of approximately 1 mA.
Since the current level is very low, it is important to use a
ceramic cap or other low leakage capacitor. Aluminum
electrolytic capacitors are not recommended for this circuit.
The ramp time from 10% to 90% of the nominal output
voltage can be determined by the following equation:
t
Cext + ǒ0.5E06Ǔ* 1.4 nF
between the input voltage (V ) and ground.
CC
Current Limit
Where: C is in Farads,
t is in Seconds
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor.
Anytime that the unit shuts down due to a fault, enable shut−
down, or recycling of input power, the timing capacitor will be
discharged and the output voltage will ramp from 0 at turn on.
Refer to Figures 9 and 11 for slew rate control and typical Slew
Rate behavior.
The current limit circuit has two limiting values, one for
short circuit events which are defined as the mode of
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10
NIS5020, NIS5021, NIS5820
Enable/Fault
Since this is a latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
an external switch and then allowed to go high or after the
input power has been recycled.
The Enable/Fault Pin is a multi−function, bidirectional
pin that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit. To use as
a simple enable pin, an open drain or open collector device
should be connected to this pin. Due to its tri−state operation,
it should not be connected to any type of logic with an
internal pull−up device. Do not connect external capacitor
directly to this pin.
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family,
a thermal shutdown of one device will cause both devices to
disable their outputs. Both devices will turn on once the fault
is removed for the auto−retry devices.
Thermal Protection
The NIS5x2x Series includes an internal temperature
sensing circuit that senses the temperature on the die of the
power FET. If the temperature reaches 175°C, the device
will shut down, and remove power from the load. Output
power can be restored by either recycling the input power or
toggling the enable pin. Power will automatically be
reapplied to the load for auto−retry devices once the die
temperature has been reduced by 45°C.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
The similar devices from different voltage families can be
configured together as shown in Figure 3 for a common
thermal shutdown.
ORDERING INFORMATION
†
Device
NIS5020MT1TXG
NIS5020MT2TXG
NIS5021MT1TXG
NIS5021MT2TXG
NIS5820MT1TXG
NIS5820MT2TXG
Marking
5020
Features
Latch
Package
Shipping
WDFN10−3x3
WDFN10−3x3
WDFN10−4x4
WDFN10−4x4
WDFN10−3x3
WDFN10−3x3
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
5020A
5021
Auto−Retry
Latch
5021A
5820
Auto−Retry
Latch
5820A
Auto−Retry
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN10 4x4, 0.8P
CASE 511DS
ISSUE A
1
DATE 23 MAY 2017
SCALE 2:1
NOTES:
B
E
A
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.20 AND 0.25 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B
ALTERNATE B−1 AND DETAIL A ALTERNATE A−1 CON-
STRUCTIONS ARE NOT APPLICABLE.
L
L
L1
ALTERNATE A−1 ALTERNATE A−2
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
PIN ONE
MILLIMETERS
REFERENCE
DIM MIN
0.70
A1 0.00
NOM MAX
A
0.75
0.03
0.80
0.05
A3
b
D
0.20 REF
0.30
4.00
3.40
4.00
A3
0.25
3.90
0.35
4.10
3.50
4.10
2.89
TOP VIEW
EXPOSED Cu
MOLD CMPD
D2 3.30
3.90
E
DETAIL B
0.10
0.08
C
A
E2 2.69
2.79
e
K
L
0.80 BSC
0.20 REF
0.40
A1
ALTERNATE B−1
ALTERNATE B−2
0.30
0.50
0.10
DETAIL B
L1 0.00
0.05
C
A3
A1
ALTERNATE
SEATING
PLANE
C
NOTE 4
CONSTRUCTIONS
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
DETAIL A
10X L
1
5
XXXX
AYWWG
G
XXXX = Specific Device Code
E2
A
= Assembly Location
= Year
Y
WW
G
= Work Week
= Pb−Free Package
K
(Note: Microdot may be in either location)
10
6
10X
b
0.10
e
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present. Some products may
not follow the Generic Marking.
C
C
A
B
0.05
NOTE 3
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT
10X
0.60
3.50
4.30
2.89
PACKAGE
OUTLINE
1
10X
0.42
0.80
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15519G
WDFN10 4X4, 0.8P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN10, 3x3, 0.5P
CASE 522AA−01
ISSUE A
DATE 02 JUL 2007
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
B
E
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
PIN ONE
REFERENCE
DIM
A
MIN
0.70
0.00
NOM
0.75
MAX
0.80
0.05
A1
A3
b
0.03
0.20 REF
0.24
2X
0.15 C
0.18
2.45
1.75
0.30
2.55
1.85
D
3.00 BSC
2.50
2X
0.15
C
D2
E
TOP VIEW
3.00 BSC
1.80
A3
E2
e
0.50 BSC
0.19 TYP
0.40
0.10
0.08
C
K
A
L
0.35
0.45
10X
C
A1
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
SIDE VIEW
D2
C
XXXXX
XXXXX
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
10X
L
e
1
5
A
L
Y
W
G
E2
(Note: Microdot may be in either location)
10X
K
10
6
b 10X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.10
0.05
C
A
B
NOTE 3
C
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.6016
1.8508 3.3048
2.1746
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON22331D
WDFN10 3X3, 0.5P
PAGE 1 OF 1
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