NIS5420 [ONSEMI]
12 Volt Electronic Fuse;
| 型号： | NIS5420 |
| 厂家： | 
ONSEMI |
| 描述： | 12 Volt Electronic Fuse |
| 文件： | 总12页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+12 Volt Electronic Fuse
Product Preview
NIS5420 Series
The NIS5420 eFuse is a cost effective, resettable fuse which can
greatly enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits. It also includes an overvoltage
clamp circuit that limits the output voltage during transients but does
not shut the unit down, thereby allowing the load circuit to continue
operation.
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4.6 AMP, 12 VOLT
ELECTRONIC FUSE
Features
• Integrated Power Device
MARKING
DIAGRAM
• Power Device Thermally Protected
• No External Current Shunt Required
• 8 V to 18 V Input Range
XXXXX
XXXXX
ALYWG
G
WDFN10
CASE 522AA
• 44 mW Typical
• Internal Charge Pump
XXX = Specific Device Code
• Internal Undervoltage Lockout Circuit
• Internal Overvoltage Clamp
• ESD Ratings: Human Body Model (HBM); 2000 V
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
(Note: Microdot may be in either location)
Typical Applications
• Hard Drives
PIN CONNECTIONS
• Mother Board Power Management
• Fan Drives
Src
Src
Src
Src
Src
GND
dV/dt
En/Flt
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
V
CC
I
LIM
SENSE
NC/I
WDFN10
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2020 − Rev. P2
NIS5420/D
NIS5420 Series
VCC
Charge
Pump
Enable
ENABLE/
FAULT
SOURCE
Current
Limit
Thermal
Shutdown
I
LIMIT
UVLO
dv/dt
dv/dt
Control
Voltage
Clamp
GND
Figure 1. Block Diagram
(NIS5420MT3, NIS5420MT4, NIS5420MT5)
VCC
Charge
Pump
Enable
ENABLE/
FAULT
SOURCE
Current
Limit
Thermal
Shutdown
I
I
LIMIT
Current
Monitor
SENSE
UVLO
dv/dt
dv/dt
Control
Voltage
Clamp
GND
Figure 2. Block Diagram
(NIS5420MT1, NIS5420MT2, NIS5420MT6, NIS5420MT7, NIS5420MT8
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2
NIS5420 Series
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
1
Function
Ground
dv/dt
Description
Negative input voltage to the device. This is used as the internal reference for the IC.
2
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal
capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this
pin to increase the ramp time. If an additional time delay is not required, this pin should be left open.
3
Enable/Fault
The enable/fault pin is a tri−state, bidirectional interface. It can be pulled to ground with external
open−drain or open collector device to shutdown the eFuse. It can also be used as a status indicator;
if the voltage level is intermediate around 1.4 V − the eFuse is in the thermal shutdown, if the voltage
level is high around 3 V − the eFuse is operating normally. Do not actively drive this pin to any
voltage. Do not connect a capacitor to this pin.
4
5
I
A resistor between this pin and the source pin sets the overload and short circuit current limit levels.
For NIS5420MT3, NIS5420MT4 and NIS5420MT5
Limit
NC
I
For NIS5420MT1, NIS5420MT2, NIS5420MT6, NIS5420MT7 and NIS5420MT8 load current monitor
SENSE
allows the system to monitor the load current in real time. Connect R
to GND.
SENSE
6−10
Source
This pin is the source of the internal power FET and the output terminal of the fuse.
Positive input voltage to the device.
11 (belly pad)
V
CC
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (V to GND, Note 1)
V
IN
−0.6 to 18
−0.6 to 25
V
CC
Transient (100 ms)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
Table 2. THERMAL RATINGS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Air
q
90
°C/W
JA
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Lead
Y
27.5
27.5
7.6
°C/W
°C/W
°C/W
J−L
J−B
J−T
max
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Board
Y
Y
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Characterization Parameter, Junction−to−Case Top
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Total Power Dissipation @ T = 25°C
P
1.39
11.1
W
mW/°C
A
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Derate above 25°C
Operating Ambient Temperature Range
Operating Junction Temperature Range
Non−operating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
−40 to 125
−40 to 150
−55 to 155
260
°C
°C
°C
°C
A
T
J
T
STG
T
L
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3
NIS5420 Series
Table 3. ELECTRICAL CHARACTERISTICS
(V = 12 V, C = 100 mF, dv/dt pin open, R
= 20 W, T = 25°C unless otherwise noted.)
CC
L
LIMIT
j
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
Delay Time (enabling of chip to I = 100 mA with 1 A resistive load)
T
dly
−
220
−
ms
D
Kelvin ON Resistance (Note 2)
J
R
35
−
44
TBD
50
−
mW
DSon
T = 140°C (Note 3)
Off State Output Voltage (V = 18 V , V = 0 V , R = R)
V
off
−
−
50
mV
A
CC
dc
GS
dc
L
2
Continuous Current (T = 25°C, 100 mm copper) (Note 3)
I
D
I
D
−
−
4.6
3.5
−
−
A
(T = 80°C, minimum copper)
A
THERMAL LATCH
Shutdown Temperature (Note 3)
T
150
−
175
45
200
−
°C
°C
ms
SD
Thermal Hysteresis (Auto−retry part only)
Thermal Shutdown Response Time
UNDER/OVERVOLTAGE PROTECTION
Output Clamping Voltage (NIS5420MT2, NIS5420MT7)
T
Hyst
T
SD
10
15
20
Res
V
12.5
13.6
−
−
14.5
16
V
V
Clamp1
V
Clamp2
Output Clamping Voltage
(NIS5420MT1, NIS5420MT4, NIS5420MT5, NIS5420MT6)
Output Clamping Response Time
T
−
−
10
ms
Clamp_Res
Undervoltage Lockout (NIS5420MT1, NIS5420MT3, NIS5420MT4,
NIS5420MT5, NIS5420MT6)
V
7.8
8.5
9.2
V
UVLO1
Undervoltage Lockout (NIS5420MT2, NIS5420MT6, NIS5420MT8)
V
6
6.5
7
V
V
UVLO2
UVLO Hysteresis
V
−
0.80
−
Hyst
CURRENT LIMIT
Kelvin Short Circuit Current Limit (R
= 20 W, Note 4)
I
I
1.68
2.1
4.2
2.52
A
A
Limit
Lim−SS
Kelvin Overload Current Limit (R
= 20 W, Note 4)
−
−
Limit
Lim−OL
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to V
Maximum Capacitor Voltage
ENABLE/FAULT
= 11.7 V)
t
−
−
1.4
−
ms
V
OUT
slew
V
−
V
CC
max
Logic Level Low (Output Disabled)
V
0.35
0.82
1.96
2.51
−
0.58
1.4
2.2
3.3
−15
−
0.81
1.95
3.0
5
V
V
in−low
in−mid
in−high
in−max
in−low
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled)
High State Maximum Voltage
V
V
V
V
V
Logic Low Sink Current (V
= 0 V)
I
−25
1.0
3.0
mA
mA
Units
enable
Logic High Leakage Current for External Switch (V
= 3.3 V)
I
−
enable
in−leak
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
Fan
−
−
TOTAL DEVICE
Bias Current (Operational)
Bias Current (Shutdown)
I
I
−
−
−
−
−
−
450
150
7.7
mA
mA
V
Bias
Bias
Minimum Operating Voltage (Notes 3 and 5)
LOAD CURRENT MONITOR
V
min
Current Monitor Sense (R
= 1 kW)
I
−
1
−
mA/A
%
SENSE
SENSE
Current Monitor Sense Accuracy
I
−10
−
10
ACC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse test: Pulse width 300 ms, duty cycle 2%.
3. Verified by design.
4. Refer to explanation of short circuit and overload conditions in application note AND9441.
5. Device will shut down prior to reaching this level based on actual UVLO trip point.
6. For output slew rate calculation with external capacitor, please refer to ”Output Slew Rate (dv/dt)” in the ”Application Information ” section
www.onsemi.com
4
NIS5420 Series
100
−40_C
25_C
10
85_C
1
0
10
20
30
40
50
60
70
80
POWER (W)
Figure 3. Thermal Trip Time vs. Power Dissipation
11
10
9
V
CC
+12 V
8
7
6
SOURCE
NIS5420MT3/
NIS5420MT4/
NIS5420MT5
R
S
4
I
LIMIT
3
ENABLE/
FAULT
GND
dv/dt
2
LOAD
1
ENABLE
GND
Figure 4. Application Circuit with Direct Current Sensing
11
10
9
8
7
6
+12 V
V
CC
SOURCE
NIS5420MT1/
NIS5420MT2/
NIS5420MT6/
NIS5420MT7/
NIS5420MT8
R
S
4
I
LIMIT
3
ENABLE
GND
I
SENSE
R
SENSE
dv/dt
2
LOAD
1
ENABLE
GND
Figure 5. Application Circuit with Direct Current Sensing
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5
NIS5420 Series
V
CC
V
CC
SOURCE
SOURCE
R
S
NIS5135
NIS5420
I
LIMIT
I
LIMIT
ENABLE/
FAULT
ENABLE/
FAULT
dv/dt
dv/dt
GND
GND
LOAD
LOAD
ENABLE
Figure 6. Common Thermal Shutdown
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6
NIS5420 Series
TYPICAL CHARACTERISTICS
5
4
3
2
2.5
2.0
1.5
1.0
1
0
0.5
0
−60 −40 −20
0
20
40
60
80 100 120
0
1
2
3
4
5
6
LOAD CURRENT (A)
T , AMBIENT TEMPERATURE (°C)
A
Figure 8. VISENSE vs. Load Current (1 kW RLIM
)
Figure 7. VISENSE vs. Ambient Temperature
18
17
16
15
14
13
12
11
10
−50 −30
−10
10
30
50
70
90
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Vclamp vs. Junction Temperature
Figure 10. Vclamp Test
60
50
40
30
20
100
90
I
D
= 1 A
80
70
60
50
40
30
20
10
0
10
0
−60 −40 −20
0
20
40
60
80
100 120
9
10
11
12
13
14
T , AMBIENT TEMPERATURE (°C)
A
V
CC
(V)
Figure 11. RDS(on) vs. VCC
Figure 12. RDS(on) vs. Ambient Temperature
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7
NIS5420 Series
TYPICAL CHARACTERISTICS
13
12
11
10
9
8
7
10
9
Kelvin I
Kelvin I
@ R
@ R
= 10 W
= 15 W
LIM_OL
LIM
8
7
Kelvin I
@
LIM_SC
= 10 W
R
LIM
LIM_OL
LIM
6
5
4
6
5
I
OL
Kelvin I
@ R
= 20 W
LIM_OL
LIM
4
3
2
1
0
3
2
Kelvin I
Kelvin I
@ R
@ R
= 15 W
= 20 W
LIM_SC
LIM
I
SC
LIM_SC
LIM
1
0
−50 −30
−10
10
30
50
70
90
5
10 15 20 25 30 35 40 45 50 55 60
(W)
T , AMBIENT TEMPERATURE (°C)
A
R
LIM
Figure 13. ILIM vs. RLIM over Ambient
Temperature
Figure 14. ILIM vs. RLIM
40
35
30
25
20
15
10
5
0
0
100
200
300
400
500
600
CAPACITANCE FROM dvdt PIN TO GND (pF)
Figure 15. Slew Rate Control
Figure 16. Tslew vs. dvdt Capacitance
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8
NIS5420 Series
APPLICATION INFORMATION
Basic Operation
therefore any bond wire resistance and external impedance
on the board have no effect on the current limit levels. In this
configuration the on resistance is slightly increased relative
to the direct sense method since only four of the source pins
are used for power.
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The dv/dt of the output voltage will be
controlled by the internal dv/dt circuit. The output voltage
will slew from 0 V to the rated output voltage in 1.4 ms,
unless additional capacitance is added to the dv/dt pin.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The current limit circuit does not shut down the part but will
reduce the conductivity of the FET to maintain a constant
current at the internally set current limit level. The input
overvoltage clamp also does not shutdown the part, but will
limit the output voltage to 13.5/15 V in the event that the
input exceeds that level.
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
voltage exceeds the overvoltage value, the gate drive of the
main FET is reduced to limit the output. This is intended to
allow operation through transients while protecting the load.
If an overvoltage condition exists for many seconds, the
device may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
Undervoltage Lockout
The undervoltage lockout circuit uses a comparator with
hysteresis to monitor the input voltage. If the input voltage
drops below the specified level, the output switch will be
switched to a high impedance state.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage (V ) and ground.
CC
Output Slew Rate dv/dt
Current Limit
The dv/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor.
The default ramp time is approximately 2 ms. This can be
modified by adding an external capacitor at the dv/dt pin.
Since the current level is very low, it is important to use a
ceramic cap or other low leakage capacitor. Aluminum
electrolytic capacitors are not recommended for this circuit.
The ramp time from 0 to the nominal output voltage can
be determined by the following equation, where t is in
seconds:
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor as well as increasing
the value and decreasing the power rating of the sense
resistor. Sense resistors are typically in the tens of ohms
range with power ratings of several milliwatts making them
very inexpensive chip resistors.
The current limit circuit has two limiting values, one for
short circuit events which are defined as the mode of
operation in which the gate is high and the FET is fully
enhanced. The overload mode of operation occurs when the
device is actively limiting the current and the gate is at an
intermediate level. For a more detailed description of this
circuit please refer to application note AND9441.
There are two methods of biasing the current limit circuit
for this device. They are shown in the two application
figures. Direct current sensing connects the sense resistor
between the current limit pin and the load. This method
includes the bond wire resistance in the current limit circuit.
This resistance has an impact on the current limit levels for
a given resistor and may vary slightly depending on the
impedance between the sense resistor and the source pins.
The on resistance of the device will be slightly lower in this
configuration since all five source pins are connected in
parallel and therefore, the effective bond wire resistance is
one fifth of the resistance for any given pin.
ǒ
Ǔ
t1.2−10.8 + 6E7 @ 20 pF ) Cext ) 0.0008
t
1.2−10.8 * 0.0008
Cext
+
* 20 pF
6E7
Where:
C is in Farads
t is in seconds
Any time that the unit shuts down due to a fault, enable
shut−down, or recycling of input power, the timing capacitor
will be discharged and the output voltage will ramp from 0
at turn on.
Enable/Fault
The Enable/Fault pin is a multi−function, bidirectional pin
that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
The other method is Kelvin sensing. This method uses one
of the source pins as the connection for the current sense
resistor. This connection senses the voltage on the die and
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9
NIS5420 Series
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit.
both devices will restart as soon as the die temperature of the
device in shutdown has been reduced to the lower thermal
limit.
To use as a simple enable pin, an open drain or open
collector device should be connected to this pin. Due to its
tri−state operation, it should not be connected to any type of
logic with an internal pullup device.
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family,
a thermal shutdown of one device will cause both devices to
disable their outputs. Both devices will turn on once the fault
is removed for the auto−retry devices.
Thermal Protection
The NIS542x includes an internal temperature sensing
circuit that senses the temperature on the die of the power
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. Output power can
be restored by either recycling the input power or toggling
the enable pin for thermally latching devices. Power will
automatically be reapplied to the load for auto−retry devices
once the die temperature has been reduced by 45°C.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
For the latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
an external switch and then allowed to go high or after the
input power has been recycled. For the auto retry devices,
3.3 V
1.95 V
0.81 V
Gnd
Figure 17. Fault/Enable Signal Levels
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10
NIS5420 Series
Startup
Blanking
12 mA
Enable SD
2.64 V
0.58 V
+
−
Enable/Fault
1.4 V
−
+
Thermal Reset
SD
Thermal
Shutdown
Thermal SD
Figure 18. Enable/Fault Simplified Circuit
ORDERING INFORMATION
Device
†
Features
UVLO
8.5
VCLAMP
15
ISENSE
Yes
Yes
No
Package
Shipping
NIS5420MT1TXG
Thermal Latching
Thermal Latching
Thermal Latching
Thermal Latching
Auto−Retry
NIS5420MT2TXG (Note 7)
NIS5420MT3TXG (Note 7)
NIS5420MT4TXG (Note 7)
NIS5420MT5TXG (Note 7)
NIS5420MT6TXG (Note 7)
NIS5420MT7TXG (Note 7)
NIS5420MT8TXG (Note 7)
6.5
13.5
NA
8.5
8.5
15
No
WDFN10
(Pb−Free)
3000 / Tape & Reel
8.5
15
No
Auto−Retry
8.5
15
Yes
Yes
Yes
Auto−Retry
6.5
13.5
NA
Auto−Retry
6.5
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
7. Production release in Q4 2020.
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11
NIS5420 Series
PACKAGE DIMENSIONS
WDFN10, 3x3, 0.5P
CASE 522AA−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
B
E
A
MILLIMETERS
PIN ONE
REFERENCE
DIM
A
MIN
0.70
0.00
NOM
0.75
MAX
0.80
0.05
A1
A3
b
0.03
0.20 REF
0.24
2X
0.15 C
0.18
2.45
1.75
0.30
2.55
1.85
D
3.00 BSC
2.50
2X
0.15
C
D2
E
TOP VIEW
3.00 BSC
1.80
A3
E2
e
0.50 BSC
0.19 TYP
0.40
0.10
0.08
C
K
A
L
0.35
0.45
10X
C
A1
SEATING
C
SIDE VIEW
D2
PLANE
SOLDERING FOOTPRINT*
2.6016
10X
L
e
1
5
E2
1.8508 3.3048
2.1746
10X
K
10
6
b 10X
10X
0.10
0.05
C
C
A
B
0.5651
10X
NOTE 3
BOTTOM VIEW
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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