NIS6452 [ONSEMI]
Electronic Fuse, 3.3/5 Volt;
| 型号： | NIS6452 |
| 厂家： | 
ONSEMI |
| 描述： | Electronic Fuse, 3.3/5 Volt |
| 文件： | 总9页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electronic Fuse, +3.3/+5 Volt
NIS6432, NIS6452
The NIS64x2 is a cost effective, resettable fuse which can greatly
enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits and to protect the input side
circuitry from reverse currents. It includes an overvoltage clamp
circuit that limits the output voltage during transients but does not shut
the unit down, thereby allowing the load circuit to continue its
operation.
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Features
• 46 mW Typical
WQFN12
CASE 510BM
• Digital and Tristate Enable
• Integrated Reverse Current Protection
• Thermally Protected
MARKING DIAGRAM
• Integrated Soft−Start Circuit
• Fast Response Overvoltage Clamp Circuit
• Internal Undervoltage Lockout Circuit
• Internal Charge Pump
XXXXX
ALYWG
G
XXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Load Current Monitor Pin
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Hard Drives
• Solid State Drives
• Mother Boards
(Note: Microdot may be in either location)
PIN CONNECTIONS
12
1
2
3
4
5
V
V
V
V
V
V
11
10
IN
IN
IN
OUT
OUT
OUT
NIS6432
NIS6452
9
8
7
13
SAS
I
LIM
IN
dV/dt
En/Fault
6
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
February, 2020 − Rev. 2
NIS6432/D
NIS6432, NIS6452
3.3V/5V
Source
VIN
VOUT
1uF
LOAD
22uF
NIS64x2
SAS Disable
SASIN
ISENSE
ILIM
RSENSE
EN/Fault
Fault
EN
RLIM
GND
dV/dt
Cdvdt
Figure 1. Typical Application Circuit
3.3V/5V
Source
VIN
VOUT
1uF
LOAD
22uF
NIS64x2
SAS Disable
SASIN
ISENSE
ILIM
RSENSE
EN/Fault
Fault
EN
RLIM
GND
dV/dt
Cdvdt
11
3
10
9
+12 Source
Source
Source
Source
Vcc
8
7
6
Source
Source
Enable/
Fault
4
2
ILIMIT
RLIM
NIS5x2x
LOAD
dV/dt
GND
1
Figure 2. Common Thermal Shutdown with another eFuse
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2
NIS6432, NIS6452
V
IN
Charge
Pump
EN/Fault
Enable/Fault
SAS
Disable
SAS
IN
Current
Limit
Current
Monitor
I
SENSE
V
Thermal
Shutdown
OUT
I
Limit
dV/dt
dV/dt
Control
UVLO
Voltage
Clamp
GND
Figure 3. Block Diagram
NIS6452 Slew Rate at 5V
300
250
200
150
100
50
y = 26.923x + 0.7692
0
0
2
4
6
8
10
12
Slew Rate (ms)
Figure 4. Slew Rate vs Cdvdt capacitance for 5V mode
Figure 5. Overload and Short Circuit Current Limit vs
RLIM
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3
NIS6432, NIS6452
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1,2,3
V
IN
Positive input voltage to the device.
4
5
SAS
When this pin is pulled high the eFuse is turned off.
IN
EN/Fault
This pin is a tri−state, bidirectional interface. It can be pulled to ground with an external open−drain
or open collector device to shut down the eFuse. It can also be used as a status indicator; if the
voltage level is intermediate (around 1.4 V), the eFuse is in thermal shutdown. If the voltage level is
high (around 3 V) the eFuse is operating normally. Do not actively drive this pin to any voltage. Do
not connect a capacitor to this pin.
6
7
I
Current Sense Pin. Connect 1 kW 1% resistor to ground.
SENSE
dV/dt
The internal dV/dt circuit controls the slew rate of the output voltage at turn on.
A resistor between this pin and ground pin sets the overload and short circuit current limit levels.
Source of the internal power FET and the output terminal of the fuse
8
I
LIM
9,10,11
12,13
V
OUT
GND
Negative input voltage to the device. This is used as the internal reference for the IC.
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (V to GND)
V
IN
−0.3 to +14
−0.3 to +15
−0.3 to 6
V
IN
Transient (100 ms)
Voltage range on EN/Fault pin
V
Voltage range on SAS pin
−0.3 to 6
IN
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL RATINGS
Thermal Resistance, Junction to Air
q
61
12
°C/W
°C/W
°C/W
W
JA
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Thermal Resistance, Junction−to−Lead
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Y
J−L
J−B
max
2
Thermal Resistance, Junction−to−Board
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Y
12
2
Total Power Dissipation @ T = 25°C
P
2.0
A
2
(4 layer High−K JEDEC JESD51−7 PCB, 100 mm , 2 oz. Cu)
Derate above 25°C
16
mW/°C
°C
Operating Ambient Temperature Range
Operating Junction Temperature Range
Non−operating Storage Temperature Range
Lead Temperature, Soldering (10 Sec)
T
−40 to 125
−40 to 150
−55 to 155
260
A
T
°C
J
T
STG
°C
T
°C
L
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4
NIS6432, NIS6452
Table 4. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V = 5 V, C = 22 F, dV/dt pin open, R
= 10 kW, T = 25°C)
A
IN
L
LIM
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
ON Resistance (Note 4)
T = 140°C (Note 5)
J
R
46
80
3
60
mW
A
DS(on)
Continuous Current (Ta = 25°C, 0.5 sq in pad) (Note 4)
(Ta = 80°C, minimum copper)
I
d
1.8
Off State Leakage (Vin = 5 V, EN = 0 V)
THERMAL LATCH
I
1
mA
leak
Shutdown Temperature (Note 1)
UNDER/OVERVOLTAGE PROTECTION
T
150
175
20
200
°C
SD
V
OUT
Maximum (V = 10 V)
NIS6432
NIS6452
V
3.6
6.3
4.4
7.0
V
ms
V
CC
out−clamp
Over Voltage Response Time
(Cout = 20 mF, Vin = 12 V, Vout < 6.5 V)
t
40
out−clamp
Undervoltage Lockout (Turn on, Voltage Going High)
NIS6432
NIS6452
V
UVLO
2.3
2.3
2.8
2.8
UVLO Hysteresis
Under Voltage Response Time, V Falling, −5 V/ms
V
0.3
2
V
ms
Hyst
t
5
10
CC
UVLO−F
UVLO−R
Under Voltage Response Time, V Rising, +5 V/ms
t
5
ms
CC
Input Voltage Slew Rate (Vin falling dV/dt)
V
10
1250
mV/ms
IN(Slew)
CURRENT LIMIT
Overload Current Limit (overload/trigger), R
= 10 kW
I
2.7
2.7
A
A
LIM
OL
Short Circuit Current Limit, R
= 10 kW
I
LIM
SC
Current Limit Response Time
LOAD CURRENT MONITORING
T
ilim
5.5
40
ms
Load Monitor Sense Current, R
REVERSE CURRENT LIMIT
Reverse Current Limit (Note 5)
= 1 kW
I
1
mA/A
SENSE
SENSE
I
1.78
10
A
REVERSE
Reverse Current Limit Response Time
(dVin/dt = −5 V/1 ms, 20 mF Load)
T
5
ms
IREVERSE
SLEW RATE CONTROL
Slew Rate (No dV/dt capacitor)
NIS6432
NIS6452
SR
1.5
1.3
ms
ENABLE/FAULT
Input Logic Level Low (Output Disabled)
Output Logic Level Low (Output Disabled)
EN
2.7
0.8
V
V
(VIL)
(VOL)
(MID)
EN
EN
Output Logic Level Mid (Thermal Fault, Output Disabled)
Output Logic Level High (Output Enabled)
Logic Low Sink Current (Venable = 0 V)
0.9
2.1
1.4
12
1.95
V
EN
V
(VOH)
(ISink)
(ILeak)
EN
20.24
1
mA
mA
Logic High Leakage Current for External Switch
(Venable = 3.3 V)
EN
Maximum Fanout for Fault Signal (Total number of chips that
can be connected to this pin for simultaneous shutdown)
EN
3
Units
(Fanout)
SAS DISABLE
Logic Level Low (Output Enabled)
Logic Level High (Output Disabled)
De−glitch Filter Delay
SAS
SAS
0.3
50
V
V
IN(VIL)
1.2
2
IN(VIH)
SAS
ms
Tdly
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5
NIS6432, NIS6452
Table 4. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V = 5 V, C = 22 F, dV/dt pin open, R
= 10 kW, T = 25°C)
A
IN
L
LIM
Characteristics
Symbol
Min
Typ
Max
Unit
TOTAL DEVICE
Bias Current
I
mA
Bias
Operational (I
= 0 A)
300
160
100
Load
Shutdown (EN = 0), (Note 2)
Fault
120
FAULT EVENTS
EN/Fault
Level
V
OUT
State
Latch
Under Voltage Lock Out
Thermal Shutdown
UVLO
TSD
EN
EN
EN
off
off
off
on
no
(VOL)
(MID)
(MID)
(VOH)
yes, (Note 1)
no, (Note 5)
N/A
Reverse Current Protection
No Fault (Vin > UVLO)
Ireverse
EN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. eFuse is latched off until the En/Fault pin is pulled low and then released, the SAS Disable pin is pulled high and then released or a power
on reset is applied to the device.
2. Does not include fan out of Enable/Fault function.
3. Pulse test: Pulse width 300 s, duty cycle 2%
4. Verified by design.
5. Once the device has entered shutdown mode due to a reverse current event, it will re−enable its output when V > V
for at least 100 ms.
IN
OUT
The slew rate SR will be applied when the output is re−enabled.
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6
NIS6432, NIS6452
APPLICATIONS INFORMATION
Basic Operation
an external switch and then allowed to go high or after the
input power has been recycled.
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
Thermal Protection
The NIS64x2 includes an internal temperature sensing
circuit that senses the temperature on the die of the power
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. Output power can
be restored by either recycling the input power or toggling
the enable pin.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The output voltage, which is controlled
by an internal dv/dt circuit, will slew from 0 V to the rated
output voltage in 1.3 ms.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The internal current limit circuit does not shut down the
part but will reduce the conductivity of the FET to maintain
a constant current at the internally set current limit level. The
input overvoltage clamp also does not shutdown the part, but
will limit the output voltage in the event that the input
exceeds the Vclamp level.
SAS Disable
The SAS Disable feature provides a digital interface to
control the output of the eFuse. When the SAS pin is
IN
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
pulled high by any external digital control circuitry the
eFuse switches to its off state. When the SAS pin is pulled
IN
low the eFuse output is turned on. All fault conditions will
be cleared when the eFuse is reset through the SAS pin.
between the input voltage (V ) and ground.
CC
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
Reverse Current Protection
The NIS64x2 monitors and protects against reverse
current events, which can be the result of a malfunction in
the power supply or noise induced in the input voltage rail
under certain load characteristics (for example, when the
load is largely capacitive).
The protection mechanism disables the eFuse’s output
and triggers when the reverse current exceeds the preset
magnitude and this condition remains for at least 7.5 ms.
The NIS64x2 automatically re−enables its output once the
input voltage exceeds the output voltage for at least 100 ms.
voltage exceeds V
, the gate drive of the main FET
out−clamp
is reduced to limit the output. This is intended to allow
operation through transients while protecting the load. If an
overvoltage condition exists for many seconds, the device
may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
Enable/Fault
The Enable/Fault Pin is a multi−function, bidirectional
pin that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit. To use as
a simple enable pin, an open drain or open collector device
should be connected to this pin. Due to its tri−state operation,
it should not be connected to any type of logic with an
internal pull−up device.
Current Limit
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor. The current limit
circuit has two limiting values, one for short circuit hold
current − I , another is overload current limit I . Refer to
SC
OL
Figure 5. for dependence of I and I vs current limit
OL
SC
resistor R
.
LIM
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family,
a thermal shutdown of one device will cause both devices to
disable their outputs. Both devices will turn on once the fault
is removed for the auto−retry devices.
Load Current Monitoring
The current monitor I
pin provides a small current
SENSE
proportional to the main device current which is flowing
through the device. This pin should have a decoupling
capacitor to filter out internal sampling noise. A resistor
connected between the I
pin and GND converts the
SENSE
I
current into a GND referenced voltage. This pin can
SENSE
be floated if the feature is not required by application.
Connect this pin to ground through 1 kOhm 1% resistor to
read the voltage corresponding to a load current.
Since this is a latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
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7
NIS6432, NIS6452
Slew Rate Control
level is very low, it is important to use a ceramic cap or other
low leakage capacitor. Aluminum electrolytic capacitors are
not recommended for this circuit. Refer to Figure 4. for the
typical ramp time vs Cdvdt capacitor. Anytime that the unit
shuts down due to a fault, enable shut−down, or recycling of
input power, the timing capacitor will be discharged and the
output voltage will ramp from 0 at turn on.
The dV/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor. The default ramp time
is approximately 1.3 ms. This pin includes an internal
current source of approximately 1 mA. Since the current
ORDERING INFORMATION
†
Device
NIS6432MT1
NIS6432MT2
NIS6452MT1
NIS6452MT2
Input Voltage
3.3 V
Marking
63L
Auto−Retry/Latch
Latch
Package
Shipping
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3.3 V
63A
Auto−Retry
Latch
WQFN 2x3
(Pb−Free)
5.0 V
65L
5.0 V
65A
Auto−Retry
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NIS6432, NIS6452
PACKAGE DIMENSIONS
WQFN12 3.0x2.0, 0.5P
CASE 510BM
ISSUE C
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