NLAS4051DR2 [ONSEMI]
Analog Multiplexer/ Demultiplexer TTL Compatible, Single-Pole, 8-Position Plus Common Off; 模拟多路复用器/多路解复用器TTL电平兼容，单刀， 8位加共关闭
| 型号： | NLAS4051DR2 |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer/ Demultiplexer TTL Compatible, Single-Pole, 8-Position Plus Common Off |
| 文件： | 总11页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAS4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
http://onsemi.com
The NLAS4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS
MARKING
DIAGRAMS
technology for lower R
resistance and improved linearity with
DS(on)
low current. This device may be operated either with a single supply or
16
dual supply up to 3.0 V to pass a 6.0 V signal without coupling
PP
SOIC−16
NLAS4051G
AWLYWW
capacitors.
D SUFFIX
CASE 751B
When operating in single supply mode, it is only necessary to tie
1
1
V
EE
, pin 7 to ground. For dual supply operation, V is tied to a
EE
negative voltage, not to exceed maximum ratings.
16
Features
NLAS
4051
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
• Improved R
Specifications
DS(on)
• Pin for Pin Replacement for MAX4051 and MAX4051A
♦ One Half the Resistance Operating at 5.0 V
• Single or Dual Supply Operation
1
1
♦ Single 2.5−5.0 V Operation, or Dual 3.0 V Operation
16
♦ With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V
Logic, No Translators Needed
♦ Address and Inhibit Logic are Over−Voltage Tolerant and May
CC
QSOP−16
QS SUFFIX
CASE 492
S4051
ALYW
1
Be Driven Up +6.0 V Regardless of V
CC
1
• Improved Linearity Over Standard HC4051 Devices
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
A
= Assembly Location
WL, L = Wafer Lot
= Year
Packages
Y
• Pb−Free Packages are Available*
WW, W = Work Week
G or G = Pb−Free Package
ORDERING INFORMATION
V
NO
15
NO
NO
13
NO ADD ADD ADD
6 C B A
CC
2
4
0
†
Shipping
Device
Package
16
14
12
11
10
9
NLAS4051DR2
SOIC−16 2500/Tape & Reel
NLAS4051DR2G
SOIC−16 2500/Tape & Reel
(Pb−Free)
NLAS4051DTR2
TSSOP−16 2500/Tape & Reel
NLAS4051DTR2G TSSOP−16 2500/Tape & Reel
(Pb−Free)
1
2
3
4
5
6
7
8
NO
NO COM NO
NO Inhibit
V
EE
GND
1
3
7
5
NLAS4051QSR
QSOP−16 2500/Tape & Reel
Figure 1. Pin Connection
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
(Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
May, 2006 − Rev. 3
NLAS4051/D
NLAS4051
NO
NO
NO
TRUTH TABLE
0
1
2
Address
B
C
A
Inhibit
ON SWITCHES*
1
X
X
X
don’t care
don’t care
don’t care
All switches open
NO
NO
3
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM−NO
COM
0
COM−NO
COM−NO
COM−NO
COM−NO
COM−NO
COM−NO
COM−NO
1
2
3
4
5
6
7
NO
NO
5
6
NO
7
ADD
ADD
ADD
C
LOGIC
Inhibit
B
A
*NO and COM pins are identical and interchangeable. Either may be considered
an input or output; signals pass equally well in either direction.
Figure 2. Logic Diagram
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Negative DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
V
−7.0 to )0.5
V
V
EE
CC
Positive DC Supply Voltage (Note 1)
V
−0.5 to )7.0
−0.5 to )7.0
(Referenced to V
)
EE
Analog Input Voltage
V
V
−0.5 to V )0.5
V
V
IS
EE
CC
Digital Input Voltage
(Referenced to GND)
V
−0.5 to 7.0
$50
IN
DC Current, Into or Out of Any Pin
Storage Temperature Range
I
mA
_C
−65 to )150
T
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
T
260
_C
_C
L
T
)150
J
SOIC
TSSOP
QSOP
ꢀ
143
164
164
°C/W
JA
Power Dissipation in Still Air,
SOIC
TSSOP
QSOP
P
500
450
450
mW
D
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
MSL
Level 1
Oxygen Index: 30% − 35%
F
UL 94 V−0 @ 0.125 in
R
Human Body Model (Note 2)
Machine Model (Note 3)
V
u2000
u200
V
ESD
Charged Device Model (Note 4)
u1000
Latchup Performance
Above V and Below GND at 125°C (Note 5)
I
$300
mA
CC
LATCHUP
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V $|V | ≤ 7.0.
CC
EE
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
NLAS4051
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
V
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
V
−5.5
GND
EE
CC
V
2.5
2.5
5.5
6.6
V
(Referenced to V
)
EE
Analog Input Voltage
V
V
V
CC
V
V
IS
EE
Digital Input Voltage
(Note 6) (Referenced to GND)
V
0
5.5
IN
Operating Temperature Range, All Package Types
T
−55
125
_C
ns/V
A
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
V
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
t , t
r f
0
0
100
20
CC
CC
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
Symbol
−55 to 25°C v85°C v125°C
V
Parameter
Condition
Unit
Minimum High−Level Input Voltage,
Address and Inhibit Inputs
V
2.5
3.0
4.5
5.5
1.75
2.1
1.75
2.1
1.75
2.1
V
IH
3.15
3.85
3.15
3.85
3.15
3.85
Maximum Low−Level Input Voltage,
Address and Inhibit Inputs
V
2.5
3.0
4.5
5.5
.45
0.9
1.35
1.65
.45
0.9
1.35
1.65
.45
0.9
1.35
1.65
V
IL
Maximum Input Leakage Current,
Address or Inhibit Inputs
V
= 6.0 or GND
I
0 V to 6.0 V
$0.1
$1.0
$1.0
ꢁ A
ꢁ A
IN
IN
Maximum Quiescent Supply Current
(per Package)
Address, Inhibit and
= V or GND
I
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
Symbol
V
V
EE
CC
−55 to 25°C v85_C v125_C
V
V
Parameter
Test Conditions
= V or V
Unit
Maximum “ON” Resistance
(Note 7)
V
V
S
R
ON
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
120
55
ꢂ
IN
IS
IL
IH
= (V to V
)
CC
EE
|I | = 10 mA
(Figures 4 thru 9)
33
37
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package |I | = 10 mA, V = 2.0 V
V
V
S
= V or V V = 2.0 V
ꢃ R
ON
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
ꢂ
IN
IS
IL
IH, IS
= ½ (V − V ), V = 3.0 V
CC
EE
IS
IS
ON Resistance Flatness
|I | = 10 mA V
= 1, 2, 3.5 V Rflat(ON) 4.5
4
2
4
2
5
3
ꢂ
S
COM
V
= 2, 0, 2 V
3.0
3.0
COM
Maximum Off−Channel
Leakage Current
Switch Off
I
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
NC(OFF)
V
V
= V or V
IN
IO
IL IH
I
NO(OFF)
= V −1.0 V or V +1.0 V
CC
EE
(Figure 17)
Maximum On−Channel
Leakage Current,
Channel− to−Channel
Switch On
I
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
COM(ON)
V
IO
= V −1.0 V or V +1.0 V
CC EE
(Figure 17)
7. At supply voltage (V ) approaching 2.5 V the analog switch on−resistance becomes extremely non−linear. Therefore, for low voltage
CC
operation it is recommended that these devices only be used to control digital signals.
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3
NLAS4051
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
−55 to 25_C
V
V
V
EE
V
CC
Min
Typ*
Symbol
Parameter
Test Conditions
v85_C v125_C Unit
Minimum Break−Before−
Make Time
V
V
= V or V
t
BBM
3.0
4.5
3.0
0.0
0.0
−3.0
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
IN
IS
IL
IH
= V
CC
R = 300
ꢂ
ꢄ C = 35 pF
L
L
(Figure 19)
*Typical Characteristics are at 25_C.
AC CHARACTERISTICS (C = 35 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
−55 to 25°C
v85°C
v125°C
V
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
Transition Time
(Address Selection Time)
(Figure 18)
t
2.5
3.0
4.5
3.0
0
0
0
22
20
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
TRANS
−3.0
Turn−on Time
(Figures 14, 15, 20, and 21)
t
2.5
3.0
4.5
3.0
0
0
0
22
18
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
ON
Inhibit to N or N
O
C
−3.0
Turn−off Time
t
2.5
3.0
4.5
3.0
0
0
0
22
18
16
16
40
28
23
23
45
30
25
25
50
35
30
28
OFF
(Figures 14, 15, 20, and 21)
Inhibit to N or N
O
C
−3.0
Typical @ 25°C, V = 5.0 V
CC
Maximum Input Capacitance, Select Inputs
C
IN
8
pF
Analog I/O
C
or C
10
10
1.0
NO
NC
Common I/O
Feedthrough
C
COM
C
(ON)
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
V
EE
CC
Symbol
V
V
25°C
Parameter
Condition
= ½ (V − V
Source Amplitude = 0 dBm
(Figures 10 and 22)
Unit
Maximum On−Channel Bandwidth or
Minimum Frequency Response
V
)
EE
BW
3.0
4.5
6.0
3.0
0.0
0.0
0.0
80
90
95
95
MHz
IS
CC
−3.0
Off−Channel Feedthrough Isolation
Maximum Feedthrough On Loss
f =100 kHz; V = ½ (V − V
Source = 0 dBm
(Figures 12 and 22)
)
EE
V
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−93
−93
−93
−93
dB
dB
IS
CC
ISO
−3.0
V
= ½ (V − V
)
EE
V
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−2
−2
−2
−2
IS
CC
ONL
Source = 0 dBm
(Figures 10 and 22)
−3.0
Charge Injection
V
R
= V to V
f
= 1 kHz, t = t = 3 ns
Q
5.0
3.0
0.0
−3.0
9.0
12
pC
%
IN
CC
EE, IS
r
f
= 0 ꢂ, C = 1000 pF, Q = C * ꢃV
IS
L
L
OUT
(Figures 16 and 23)
Total Harmonic Distortion THD + Noise
f
= 1 MHz, R = 10 Kꢂ, C = 50 pF,
THD
IS
L
L
V
V
= 5.0 V sine wave
6.0
3.0
0.0
−3.0
0.10
0.05
IS
IS
PP
= 6.0 V sine wave
PP
(Figure 13)
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4
NLAS4051
100
10
100
80
60
40
2.0 V
1
0.1
0.01
V
= 3.0 V
CC
3.0 V
4.5 V
5.5 V
0.001
0.0001
20
0
V
= 5.0 V
CC
0.00001
−40
−20
0
20
60
80
100
120
−4.0
−2.0
0
2.0
(VDC)
4.0
6.0
Temperature (°C)
V
IS
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
90
80
70
60
50
40
30
20
10
125°C
85°C
125°C
25°C
40
30
25°C
85°C
20
10
−55°C
−55°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
VCom (V)
VCom (V)
Figure 5. Typical On Resistance
VCC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
25
20
15
10
25
125°C
125°C
85°C
85°C
20
15
25°C
−55°C
10
5
25°C
−55°C
5
0
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0
VCom (V)
3.5 4.0 4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCom (V)
Figure 7. Typical On Resistance
CC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
V
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5
NLAS4051
25
20
15
10
5
125°C
85°C
−55°C
25°C
0
−4
−2
0
2
4
VCom (V)
Figure 9. Typical On Resistance
VCC = 3.3 V, VEE = −3.3 V
90
50
40
30
20
10
0
72
54
36
18
0
BANDWIDTH (ON−RESPONSE)
PHASE SHIFT
−10
−20
−18
−36
−30
−40
−50
−54
−72
−90
0.1
1.0
10
100
0.1
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth, VCC = 5.0 V
Figure 11. Phase Shift, VCC = 5.0 V
0
0
−10
−20
3.0
−30
−40
−50
−60
−70
−80
−90
−100
5.5
4.5
0.1
$3.3
0.01
0.1
1.0
10
100
10
100
1000
10000
10000
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 12. Off Isolation, VCC = 5.0 V
Figure 13. Total Harmonic Distortion
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6
NLAS4051
30
25
30
25
20
15
10
5
T = 25_C
V
= 4.5 V
A
CC
20
15
10
t
(ns)
ON
t
ON
t
t
(ns)
OFF
OFF
5
0
0
−55
2.5
3
3.5
V
4
4.5
5
−40
25
Temperature (°C)
85
125
(VOLTS)
CC
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
2.5
2.0
1.5
1.0
0.5
100
10
1
V
= 5 V
CC
I
COM(ON)
0.1
I
COM(OFF)
V
= 3 V
CC
0.01
0
V
= 5.0 V
85
CC
I
NO(OFF)
−0.5
0.001
0
1
2
3
4
5
−55
−20
25
70
125
TEMPERATURE (°C)
V
(V)
COM
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
V
CC
V
Output
CC
Input
50%
50%
V
OUT
0.1 ꢁ F
0 V
V
EE
300
ꢂ
35 pF
V
CC
90%
Output
V
Address Select Pin
10%
EE
t
t
trans
trans
Figure 18. Channel Selection Propagation Delay
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7
NLAS4051
V
CC
DUT
Input
GND
V
Output
CC
V
OUT
0.1 ꢁ F
t
BMM
300
ꢂ
35 pF
90%
90% of V
OH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break−Before−Make)
V
CC
DUT
Input
50%
50%
90%
V
0 V
CC
Output
V
OUT
0.1 ꢁ F
V
OH
Open
300
ꢂ
35 pF
90%
Output
GND
Enable
Input
t
t
OFF
ON
Figure 20. tON/tOFF
V
V
CC
CC
Input
0 V
50%
50%
DUT
300
ꢂ
Output
V
OUT
V
CC
Open
35 pF
Output
V
10%
10%
OL
Enable
Input
t
t
ON
OFF
Figure 21. tON/tOFF
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8
NLAS4051
50
ꢂ
DUT
Reference
Input
50 ꢂ Generator
Transmitted
Output
50
ꢂ
Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off
channel. On loss is the bandwidth of an On switch. V , Bandwidth and V
are independent of the input
ISO
ONL
signal direction.
V
OUT
= Off Channel Isolation = 20 Log ǒ Ǔ
V
V
for V at 100 kHz
IN
ISO
V
IN
OUT
V
= On Channel Loss = 20 Log ǒ Ǔ for V at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
ONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
V
CC
V
Output
Open
IN
GND
C
L
Output
Off
ꢃ V
OUT
Off
On
V
IN
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
+3.0 V
V
V
CC
CC
16
16
V
V
EE
EE
7
7
8
GND
GND
8
−3.0 V
Figure 24. 5.0 Volts Single Supply
CC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = −3.0 V
V
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NLAS4051
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T B
TSSOP−16
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
0.25 (0.010)
S
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
0.15 (0.006) T U
A
M
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
−V−
N
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
DETAIL E
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
http://onsemi.com
10
NLAS4051
PACKAGE DIMENSIONS
QSOP−16
QS SUFFIX
CASE 492−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
−A−
Q
R
H x 45
_
U
RAD.
0.013 X 0.005
DP. MAX
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
−B−
MOLD PIN
MARK
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
F
MAX
0.196
0.157
0.068
0.012
0.035
MIN
4.80
3.81
1.55
0.20
0.41
MAX
4.98
3.99
1.73
0.31
0.89
0.189
0.150
0.061
0.008
0.016
RAD.
0.005−0.010
TYP
G
H
J
0.025 BSC
0.64 BSC
0.008 0.018
0.0098 0.0075
0.20
0.249
0.10
5.84
0
0.46
0.191
0.25
6.20
8
G
L
K
L
0.004
0.230
0
0.010
0.244
8
P
DETAIL E
M
0.25 (0.010)
T
M
N
P
_
_
_
_
0
0.007
7
0.011
0
0.18
7
0.28
_
_
_
_
Q
R
U
V
0.020 DIA
0.51 DIA
0.025
0.025
0
0.035
0.035
8
0.64
0.64
0
0.89
0.89
8
V
K
_
_
_
_
C
N 8 PL
−T−
D16 PL
0.25 (0.010)
SEATING
PLANE
M
S
S
A
T
B
J
M
F
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 421 33 790 2910
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Order Literature: http://www.onsemi.com/orderlit
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For additional information, please contact your local
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