NLAS4051SDTR2G [ONSEMI]
Analog Multiplexer/ Demultiplexer; 模拟多路复用器/多路解复用器
| 型号： | NLAS4051SDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer/ Demultiplexer |
| 文件： | 总11页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAS4051S
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
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The NLAS4051S is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS
MARKING
DIAGRAM
technology for lower R
resistance and improved linearity with
DS(on)
low current. This device may be operated either with a single supply or
16
16
dual supply up to 3.0 V to pass a 6.0 V signal without coupling
PP
capacitors.
NLAS
4051
ALYWG
G
1
When operating in single supply mode, it is only necessary to tie
TSSOP−16
DT SUFFIX
CASE 948F
V , pin 7 to ground. For dual supply operation, V is tied to a
EE
EE
negative voltage, not to exceed maximum ratings.
1
Features
• Improved R
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Specifications
DS(on)
• Pin for Pin Replacement for MAX4051 and MAX4051A
♦ One Half the Resistance Operating at 5.0 V
• Single or Dual Supply Operation
(Note: Microdot may be in either location)
♦ Single 2.5−5.0 V Operation, or Dual 3.0 V Operation
♦ With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V
CC
Logic, No Translators Needed
♦ Address and Inhibit Logic are Over−Voltage Tolerant and May
ORDERING INFORMATION
Be Driven Up +6.0 V Regardless of V
CC
†
Shipping
Device
Package
• Improved Linearity Over Standard HC4051 Devices
• Space Saving TSSOP Package
NLAS4051SDTR2G TSSOP−16 2500/Tape & Reel
(Pb−Free)
• This is a Pb−Free Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
V
NO
15
NO
NO
13
NO ADD ADD ADD
6 C B A
CC
2
4
0
16
14
12
11
10
9
1
2
3
4
5
6
Inhibit
7
8
NO
NO COM NO
NO
V
EE
GND
1
3
7
5
Figure 1. Pin Connection
(Top View)
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
May, 2008 − Rev. 0
NLAS4051S/D
NLAS4051S
TRUTH TABLE
NO
NO
NO
0
1
2
Address
ON
SWITCHES*
C
B
A
Inhibit
1
X
X
X
All switches
open
don’t care don’t care don’t care
NO
NO
3
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM−NO
0
COM
COM−NO
1
COM−NO
2
NO
NO
5
6
COM−NO
3
COM−NO
4
COM−NO
5
NO
7
COM−NO
6
ADD
ADD
ADD
C
LOGIC
Inhibit
B
A
COM−NO
7
*NO and COM pins are identical and interchangeable. Either may
be considered an input or output; signals pass equally well in
either direction.
Figure 2. Logic Diagram
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
Negative DC Supply Voltage
Positive DC Supply Voltage (Note 1)
(Referenced to GND)
(Referenced to GND)
V
EE
CC
−7.0 to )0.5
V
−0.5 to )7.0
−0.5 to )7.0
V
(Referenced to V
)
EE
Analog Input Voltage
V
V
EE
−0.5 to V )0.5
V
V
IS
CC
Digital Input Voltage
(Referenced to GND)
V
IN
−0.5 to 7.0
$50
DC Current, Into or Out of Any Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
I
mA
°C
T
STG
−65 to )150
260
T
°C
L
T
)150
°C
J
ꢀ
164
°C/W
mW
JA
Power Dissipation in Still Air
Moisture Sensitivity
P
450
D
MSL
Level 1
Flammability Rating
Oxygen Index: 30% − 35%
F
R
UL 94 V−0 @ 0.125 in
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
V
ESD
u2000
u200
u1000
V
Latchup Performance
Above V and Below GND at 125°C (Note 5)
I
$300
mA
CC
LATCHUP
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V $|V | ≤ 7.0.
CC
EE
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
NLAS4051S
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
V
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
V
EE
CC
−5.5
GND
V
2.5
2.5
5.5
6.6
V
(Referenced to V
)
EE
Analog Input Voltage
V
V
V
CC
V
V
IS
EE
Digital Input Voltage
(Note 6) (Referenced to GND)
V
IN
0
5.5
Operating Temperature Range, All Package Types
T
A
−55
125
°C
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
V
CC
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
t , t
r f
0
0
100
20
ns/V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
Symbol
−55 to 25°C v85°C v125°C
V
Parameter
Condition
Unit
Minimum High−Level Input Voltage,
Address and Inhibit Inputs
V
IH
2.5
3.0
4.5
5.5
1.75
2.1
1.75
2.1
1.75
2.1
V
3.15
3.85
3.15
3.85
3.15
3.85
Maximum Low−Level Input Voltage,
Address and Inhibit Inputs
V
IL
2.5
3.0
4.5
5.5
.45
0.9
1.35
1.65
.45
0.9
1.35
1.65
.45
0.9
1.35
1.65
V
Maximum Input Leakage Current,
Address or Inhibit Inputs
V
= 6.0 or GND
I
0 V to 6.0 V
$0.1
$1.0
$1.0
ꢁ A
ꢁ A
IN
IN
Maximum Quiescent Supply Current
(per Package)
Address, Inhibit and
= V or GND
I
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbol
Guaranteed Limit
V
CC
V
EE
V
V
−55 to 25°C v85°C v125°C
Parameter
Test Conditions
= V or V
Unit
Maximum “ON” Resistance
(Note 7)
V
V
S
R
ON
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
120
55
ꢂ
IN
IS
IL
IH
= (V to V
)
EE
CC
|I | = 10 mA
33
37
(Figures 4 thru 9)
Maximum Difference in “ON”
Resistance Between Any Two
V
V
S
= V or V V = 2.0 V
ꢃ R
ON
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
ꢂ
IN
IS
IL
IH, IS
= ½ (V − V ), V = 3.0 V
CC
EE
IS
Channels in the Same Package |I | = 10 mA, V = 2.0 V
IS
ON Resistance Flatness
|I | = 10 mA V
= 1, 2, 3.5 V
COM
R
flat(ON)
4.5
3.0
4
2
4
2
5
3
ꢂ
S
COM
V
= 2, 0, 2 V
3.0
Maximum Off−Channel
Leakage Current
Switch Off
I
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
NC(OFF)
V
IN
V
IO
= V or V
IL IH
CC
I
NO(OFF)
= V −1.0 V or V +1.0 V
EE
(Figure 17)
Maximum On−Channel
Leakage Current,
Channel− to−Channel
Switch On
I
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
COM(ON)
V
= V −1.0 V or V +1.0 V
CC EE
IO
(Figure 17)
7. At supply voltage (V ) approaching 2.5 V the analog switch on−resistance becomes extremely non−linear. Therefore, for low voltage
CC
operation it is recommended that these devices only be used to control digital signals.
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3
NLAS4051S
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
−55 to 25°C
V
CC
V
EE
V
V
Min
Typ*
Symbol
Parameter
Test Conditions
v85°C v125°C Unit
Minimum Break−Before−
Make Time
V
V
= V or V
t
BBM
3.0
4.5
3.0
0.0
0.0
−3.0
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
IN
IS
L
IL
IH
= V
CC
R = 300
ꢂ
ꢄ C = 35 pF
L
(Figure 19)
*Typical Characteristics are at 25°C.
AC CHARACTERISTICS (C = 35 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
−55 to 25°C
v85°C
v125°C
V
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
Parameter
Symbol
Unit
Transition Time
(Address Selection Time)
(Figure 18)
t
2.5
3.0
4.5
3.0
0
0
22
20
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
TRANS
0
−3.0
Turn−on Time
t
2.5
3.0
4.5
3.0
0
0
22
18
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
ON
(Figures 14, 15, 20, and 21)
Inhibit to N or N
0
O
C
−3.0
Turn−off Time
t
2.5
3.0
4.5
3.0
0
0
0
22
18
16
16
40
28
23
23
45
30
25
25
50
35
30
28
OFF
(Figures 14, 15, 20, and 21)
Inhibit to N or N
O
C
−3.0
Typical @ 255C, V = 5.0 V
CC
Maximum Input Capacitance, Select Inputs
C
8
pF
IN
Analog I/O
C
or C
10
10
1.0
NO
NC
Common I/O
Feedthrough
C
COM
C
(ON)
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
CC
V
EE
Symbol
V
V
25°C
Parameter
Condition
= ½ (V − V
Source Amplitude = 0 dBm
(Figures 10 and 22)
Unit
Maximum On−Channel Bandwidth or
Minimum Frequency Response
V
IS
)
EE
BW
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
80
90
95
95
MHz
CC
Off−Channel Feedthrough Isolation
f =100 kHz; V = ½ (V − V
)
V
3.0
4.5
6.0
3.0
0.0
0.0
−93
−93
−93
−93
dB
dB
IS
CC
EE
ISO
Source = 0 dBm
(Figures 12 and 22)
0.0
−3.0
Maximum Feedthrough On Loss
V
IS
= ½ (V − V
)
V
ONL
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−2
−2
−2
−2
CC
EE
Source = 0 dBm
(Figures 10 and 22)
Charge Injection
V
= V to V
f
= 1 kHz, t = t = 3 ns
Q
5.0
3.0
0.0
9.0
12
pC
%
IN
IS
CC
EE, IS
r
f
R
= 0 ꢂ, C = 1000 pF, Q = C * ꢃV
−3.0
L
L
OUT
(Figures 16 and 23)
Total Harmonic Distortion THD + Noise
f
IS
= 1 MHz, R = 10 Kꢂ, C = 50 pF,
THD
L
L
V
IS
V
IS
= 5.0 V sine wave
6.0
3.0
0.0
−3.0
0.10
0.05
PP
= 6.0 V sine wave
PP
(Figure 13)
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4
NLAS4051S
100
10
100
80
60
2.0 V
1
0.1
0.01
40
20
0
V
= 3.0 V
CC
3.0 V
4.5 V
5.5 V
0.001
0.0001
V
= 5.0 V
CC
0.00001
−40
−20
0
20
60
80
100
120
−4.0
−2.0
0
2.0
(VDC)
4.0
6.0
Temperature (°C)
V
IS
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
90
80
70
60
50
40
30
20
10
125°C
85°C
125°C
25°C
40
30
25°C
85°C
20
10
−55°C
−55°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
(V)
1.5
2.0
V
V
(V)
Com
Com
Figure 5. Typical On Resistance
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
V
CC = 2.0 V, VEE = 0 V
25
20
15
10
25
125°C
125°C
85°C
85°C
20
15
25°C
10
5
25°C
−55°C
−55°C
5
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0
(V)
3.5 4.0 4.5
0
0.5
1
1.5
2
2.5
V
3
3.5
4
4.5
5
5.5
V
Com
(V)
Com
Figure 7. Typical On Resistance
CC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
V
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5
NLAS4051S
25
20
15
10
5
125°C
85°C
−55°C
25°C
0
−4
−2
0
2
4
V
Com
(V)
Figure 9. Typical On Resistance
VCC = 3.3 V, VEE = −3.3 V
90
50
40
30
20
10
0
72
54
36
18
0
BANDWIDTH (ON−RESPONSE)
PHASE SHIFT
−10
−20
−18
−36
−30
−40
−50
−54
−72
−90
0.1
1.0
10
100
0.1
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth, VCC = 5.0 V
Figure 11. Phase Shift, VCC = 5.0 V
0
0
−10
−20
3.0
−30
−40
−50
−60
−70
−80
−90
−100
5.5
4.5
0.1
$3.3
0.01
0.1
1.0
10
100
10
100
1000
10000
10000
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 12. Off Isolation, VCC = 5.0 V
Figure 13. Total Harmonic Distortion
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6
NLAS4051S
30
25
20
15
10
30
25
20
15
10
5
T = 25°C
V
CC
= 4.5 V
A
t
(ns)
ON
t
ON
t
t
(ns)
3.5
OFF
5
0
OFF
0
2.5
3
4
4.5
5
−55
−40
25
Temperature (°C)
85
125
V
CC
(VOLTS)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
2.5
2.0
1.5
1.0
0.5
100
10
1
V
= 5 V
CC
I
COM(ON)
0.1
I
COM(OFF)
V
CC
= 3 V
0.01
0
V
CC
= 5.0 V
85
I
NO(OFF)
−0.5
0.001
0
1
2
3
4
5
−55
−20
25
70
125
TEMPERATURE (°C)
V
COM
(V)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
V
CC
V
Output
CC
Input
50%
50%
V
OUT
0.1 ꢁ F
0 V
V
EE
300
ꢂ
35 pF
V
CC
90%
Output
V
Address Select Pin
10%
EE
t
t
trans
trans
Figure 18. Channel Selection Propagation Delay
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7
NLAS4051S
V
CC
DUT
Input
GND
V
CC
Output
V
OUT
0.1 ꢁ F
t
BMM
300
ꢂ
35 pF
90%
90% of V
OH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break−Before−Make)
V
CC
DUT
Input
50%
50%
90%
V
CC
0 V
Output
V
OUT
0.1 ꢁ F
V
OH
Open
300
ꢂ
35 pF
90%
Output
GND
Enable
Input
t
t
OFF
ON
Figure 20. tON/tOFF
V
CC
V
CC
Input
0 V
50%
50%
DUT
300
ꢂ
Output
V
OUT
V
CC
Open
35 pF
Output
V
10%
10%
OL
Enable
Input
t
t
ON
OFF
Figure 21. tON/tOFF
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8
NLAS4051S
50
ꢂ
DUT
Reference
Input
50 ꢂ Generator
Transmitted
Output
50
ꢂ
Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off
channel. On loss is the bandwidth of an On switch. V , Bandwidth and V
are independent of the input
ISO
ONL
signal direction.
V
OUT
= Off Channel Isolation = 20 Log ǒ Ǔ for V
V
V
at 100 kHz
ISO
IN
V
IN
OUT
V
= On Channel Loss = 20 Log ǒ Ǔ for V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
ONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
V
CC
V
IN
Output
Open
GND
C
L
Output
Off
ꢃ V
OUT
Off
On
V
IN
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
+3.0 V
V
CC
V
CC
16
16
V
V
EE
EE
7
8
7
8
GND
GND
−3.0 V
Figure 24. 5.0 Volts Single Supply
CC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = −3.0 V
V
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NLAS4051S
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
M
S
S
0.10 (0.004)
T U
V
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T U
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
F
C
D
F
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
NLAS4051S
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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