NLHV4052DR2G [ONSEMI]
Analog Multiplexers/Demultiplexers;型号: | NLHV4052DR2G |
厂家: | ONSEMI |
描述: | Analog Multiplexers/Demultiplexers |
文件: | 总11页 (文件大小:128K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NLHV4051, NLHV4052,
NLHV4053
Analog
Multiplexers/Demultiplexers
The NLHV4051, NLHV4052, and NLHV4053 analog multiplexers
are digitally−controlled analog switches. The NLHV4051 effectively
implements an SP8T solid state switch, the NLHV4052 a DP4T, and
the NLHV4053 a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
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Features
1
1
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V − V ) = 3.0 to 18 V
DD
EE
MARKING DIAGRAMS
Note: V must be ≤ V
EE
SS
16
• Linearized Transfer Characteristics
NLHVG
405x
AWLYWW
• Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
1
SOIC−16
• For Lower R , Use the HC4051, HC4052, or HC4053 High−Speed
ON
CMOS Devices
16
1
• These Devices are Pb−Free and are RoHS Compliant
NLHV
405x
ALYWG
G
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
−0.5 to +18.0
V
TSSOP−16
(Referenced to V , V ≥ V )
EE
SS
EE
V ,
Input or Output Voltage Range
(DC or Transient) (Referenced to V for
−0.5 to V + 0.5
V
in
DD
x
A
WL, L
Y
= 1, 2, or 3
= Assembly Location
= Wafer Lot
V
out
SS
Control Inputs and V for Switch I/O)
EE
I
in
Input Current (DC or Transient)
per Control Pin
+10
mA
= Year
WW, W = Work Week
G or G
= Pb−Free Package
I
Switch Through Current
25
500
mA
mW
°C
SW
(Note: Microdot may be in either location)
P
Power Dissipation per Package (Note 1)
Ambient Temperature Range
D
T
−55 to +125
−65 to +150
260
A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
T
Storage Temperature Range
°C
stg
T
Lead Temperature (8−Second Soldering)
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained to
in
out
the range V ≤ (V or V ) ≤ V .
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
V
, V or V ). Unused outputs must be left open.
SS EE
DD
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April, 2017 − Rev. 0
NLHV4051/D
NLHV4051, NLHV4052, NLHV4053
NLHV4051
NLHV4052
NLHV4053
8−Channel Analog
Multiplexer/Demultiplexer
Dual 4−Channel Analog
Multiplexer/Demultiplexer
Triple 2−Channel Analog
Multiplexer/Demultiplexer
6
11
10
9
INHIBIT
A
6
CONTROLS 10
INHIBIT
A
6
11
10
9
INHIBIT
A
14
15
X
Y
CONTROLS
CONTROLS
X
Y
13
B
C
9
12
14
15
B
X0
B
C
COMMONS
OUT/IN
X1
X2
X3
Y0
Y1
Y2
Y3
X0
X1
13
14
15
12
1
X0
X1
X2
X3
X4
X5
X6
X7
12
13
2
COMMONS
OUT/IN
X
3
COMMON
SWITCHES
IN/OUT
SWITCHES
IN/OUT
11
Y0
Y1
Z0
Z1
SWITCHES
IN/OUT
1
1
5
OUT/IN
3
Z
4
5
5
2
3
2
4
4
V
= PIN 16
= PIN 8
= PIN 7
V
= PIN 16
= PIN 8
= PIN 7
V
DD
= PIN 16
= PIN 8
= PIN 7
DD
DD
V
V
V
SS
EE
SS
SS
V
V
V
EE
EE
Note: Control Inputs referenced to V , Analog Inputs and Outputs reference to V . V must be ≤ V
SS
.
SS
EE
EE
PIN ASSIGNMENT
NLHV4052
NLHV4051
NLHV4053
X4
X6
X
1
2
3
4
5
6
7
8
16
V
DD
Y0
Y2
Y
1
2
3
4
5
6
7
8
16
V
DD
Y1
Y0
Z1
Z
1
2
3
4
5
6
7
8
16
15
14
V
Y
X
DD
15 X2
14 X1
13 X0
12 X3
15 X2
14 X1
X7
X5
INH
Y3
Y1
INH
13
X
13 X1
12 X0
12 X0
11 X3
Z0
INH
11
10
9
A
B
C
11
10
9
A
B
C
V
EE
V
EE
10
9
A
B
V
EE
V
SS
V
SS
V
SS
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2
NLHV4051, NLHV4052, NLHV4053
ELECTRICAL CHARACTERISTICS
−55_C
25_C
Typ
125_C
(Note 2)
Min Max Min
Max Min Max
Characteristic
Symbol
V
DD
Test Conditions
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
Power Supply Voltage
Range
V
DD
−
3.0
18
3.0
−
18
3.0
18
V
V
DD
– 3.0 ≥ VSS ≥ V
EE
Quiescent Current Per
Package
I
5.0 Control Inputs:
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
DD
10
15
V
= V or V
,
in
SS
DD
Switch I/O: V v V
v
EE
I/O
v
V
DD
, and DV
switch
500 mV (Note 3)
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
5.0 T = 25_C only (The
mA
D(AV)
A
(0.07 mA/kHz) f + I
(0.20 mA/kHz) f + I
(0.36 mA/kHz) f + I
DD
DD
DD
10
15
channel component,
Typical
(V – V )/R , is
in out on
not included.)
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to V
)
SS
Low−Level Input Voltage
High−Level Input Voltage
V
5.0
10
15
R
= per spec,
on
= per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
V
IL
IH
in
I
off
V
5.0
10
15
R
= per spec,
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
on
I
off
= per spec
Input Leakage Current
Input Capacitance
I
15
−
V
in
= 0 or V
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mA
DD
C
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to V
)
EE
Recommended
Peak−to−Peak Voltage
Into or Out of the Switch
V
−
Channel On or Off
0
V
0
0
−
−
V
0
0
V
V
PP
I/O
DD
DD
DD
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 5)
DV
−
Channel On
0
600
600
300
mV
switch
Output Offset Voltage
ON Resistance
V
−
V
= 0 V, No Load
−
−
−
10
−
−
−
mV
OO
in
R
5.0 DV
10
15
v 500 mV
(Note 3) V = V or V
in IL IH
(Control), and V
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
on
switch
=
in
0 to V (Switch)
DD
DON Resistance Between
Any Two Channels in the
Same Package
DR
5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
on
Off−Channel Leakage
Current (Figure 10)
I
off
15
V
= V or V
IH
−
100
−
0.05
100
−
1000 nA
in
IL
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
C
C
−
−
Inhibit = V
−
−
−
10
−
−
−
pF
pF
I/O
DD
Capacitance, Common O/I
Inhibit = V
O/I
DD
(NLHV4051)
(NLHV4052)
(NLHV4053)
−
−
−
−
−
−
−
−
−
60
32
17
−
−
−
−
−
−
−
−
−
Capacitance, Feedthrough
(Channel Off)
C
−
−
Pins Not Adjacent
Pins Adjacent
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
pF
I/O
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV
) > 600 mV (> 300 mV at high temperature), excessive V current may be drawn, i.e. the
switch
DD
current out of the switch may contain both V
and switch input components. The reliability of the device will be unaffected unless the
DD
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
NLHV4051, NLHV4052, NLHV4053
ELECTRICAL CHARACTERISTICS (Note 4) (C = 50 pF, T = 25_C) (V v V unless otherwise indicated)
L
A
EE
SS
V
DD
– V
Typ (Note 5)
EE
Vdc
All Types
Characteristic
Symbol
Max
Unit
Propagation Delay Times (Figure 6)
t
, t
ns
PLH PHL
Switch Input to Switch Output (R = 1 kW)
L
NLHV4051
t
t
t
, t
= (0.17 ns/pF) C + 26.5 ns
5.0
10
15
35
15
12
90
40
30
PLH PHL
L
, t
= (0.08 ns/pF) C + 11 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 9.0 ns
L
PLH PHL
NLHV4052
ns
ns
ns
t
t
t
, t
= (0.17 ns/pF) C + 21.5 ns
5.0
10
15
30
12
10
75
30
25
PLH PHL
L
, t
= (0.08 ns/pF) C + 8.0 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 7.0 ns
L
PLH PHL
NLHV4053
t
t
t
, t
= (0.17 ns/pF) C + 16.5 ns
5.0
10
15
25
8.0
6.0
65
20
15
PLH PHL
L
, t
= (0.08 ns/pF) C + 4.0 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 3.0 ns
L
PLH PHL
Inhibit to Output (R = 10 kW, V = V
)
t
, t
,
L
EE
SS
PHZ PLZ
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
NLHV4051
t
, t
PZH PZL
5.0
10
15
350
170
140
700
340
280
NLHV4052
NLHV4053
5.0
10
15
300
155
125
600
310
250
ns
ns
ns
5.0
10
15
275
140
110
550
280
220
Control Input to Output (R = 1 kW, V = V
)
t
, t
L
EE
SS
PLH PHL
NLHV4051
5.0
10
15
360
160
120
720
320
240
NLHV4052
5.0
10
15
325
130
90
650
260
180
ns
ns
NLHV4053
5.0
10
15
300
120
80
600
240
160
Second Harmonic Distortion
−
10
0.07
−
%
(R = 10KW, f = 1 kHz) V = 5 V
L
in
PP
Bandwidth (Figure 7)
BW
10
17
−
MHz
(R = 50 W, V = 1/2 (V −V ) p−p, C = 50pF
L
in
DD
EE
L
20 Log (V /V ) = − 3 dB)
out in
Off Channel Feedthrough Attenuation (Figure 7)
R = 1KW, V = 1/2 (V − V ) p−p
−
10
–50
−
dB
L
in
DD
EE
f
f
f
= 4.5 MHz — NLHV4051
= 30 MHz — NLHV4052
= 55 MHz — NLHV4053
in
in
in
Channel Separation (Figure 8)
(R = 1 kW, V = 1/2 (V −V ) p−p,
−
−
10
10
–50
75
−
−
dB
L
in
DD
EE
f
in
= 3.0 MHz
Crosstalk, Control Input to Common O/I (Figure 9)
mV
(R = 1 kW, R = 10 kW
1
L
Control t
= t
THL
= 20 ns, Inhibit = V
)
TLH
SS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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4
NLHV4051, NLHV4052, NLHV4053
V
DD
V
DD
V
DD
IN/OUT
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
V
EE
Figure 1. Switch Circuit Schematic
16
V
V
TRUTH TABLE
DD
Control Inputs
Select
INHꢀꢀ6
BINARY TO 1-OF-8
DECODER WITH
INHIBIT
ON Switches
Aꢀ11
Bꢀ10
Cꢀꢀ9
LEVEL
CONVERTER
C*
B
A
NLHV4051 NLHV4052
NLHV4053
Inhibit
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
X0
X1
X2
X3
Z0 Y0 X0
Z0 Y0 X1
Z0 Y1 X0
Z0 Y1 X1
8
V
SS
7
EE
X0ꢀ13
X1ꢀ14
X2ꢀ15
X3ꢀ12
X4ꢀꢀ1
X5ꢀꢀ5
X6ꢀꢀ2
X7ꢀꢀ4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
3ꢀX
1
x
x
x
None
None
None
*Not applicable for MC14052
x = Don’t Care
Figure 2. NLHV4051 Functional Diagram
16
V
DD
16
V
DD
INHꢀꢀ6
Aꢀ10
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INHꢀꢀ6
Aꢀ11
Bꢀ10
BINARY TO 1-OF-2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
Bꢀꢀ9
Cꢀꢀ9
8
V
SS
7
V
EE
X0ꢀ12
X1ꢀ14
X2ꢀ15
X3ꢀ11
Y0ꢀꢀ1
Y1ꢀꢀ5
Y2ꢀꢀ2
Y3ꢀꢀ4
8
V
SS
7
V
EE
13ꢀX
3ꢀꢀY
X0ꢀ12
X1ꢀ13
Y0ꢀꢀ2
Y1ꢀꢀ1
Z0ꢀꢀ5
Z1ꢀꢀ3
14ꢀX
15ꢀY
4ꢀꢀZ
Figure 3. NLHV4052 Functional Diagram
Figure 4. NLHV4053 Functional Diagram
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5
NLHV4051, NLHV4052, NLHV4053
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
V
out
LOAD
V
C
INH
R
L
L
SOURCE
V
DD
V
EE
V
EE
V
DD
Figure 5. DV Across Switch
Figure 6. Propagation Delay Times,
Control and Inhibit to Output
A, B, and C inputs used to turn ON
or OFF the switch under test.
R
L
A
B
C
A
B
ON
V
out
C
INH
C = 50 pF
L
R
V
SS
L
OFF
INH
V
out
V
in
R
L
C
= 50 pF
L
V
DD
- V
2
EE
V
DD
- V
2
EE
V
in
Figure 7. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST
V
DD
EE
V
A
B
C
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
V
V
V
EE
out
R
DD
INH
C = 50 pF
L
L
R1
V
V
EE
COMMON
DD
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 in the MC14016B data sheet.
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6
NLHV4051, NLHV4052, NLHV4053
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
X-Y
PLOTTER
V
DD
V
EE
= V
SS
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350
300
350
300
250
200
150
100
250
200
150
T = 125°C
A
T = 125°C
A
100
25°C
25°C
-ꢁ55°C
-ꢁ55°C
50
0
50
0
-ꢁ10 -ꢁ8.0 -ꢁ6.0 -ꢁ4.0 -ꢁ2.0
-ꢁ10 -ꢁ8.0 -ꢁ6.0 -ꢁ4.0 -ꢁ2.0
0
0.2 4.0
6.0 8.0
10
0
0.2 4.0
6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 12. VDD = 7.5 V, VEE = − 7.5 V
Figure 13. VDD = 5.0 V, VEE = − 5.0 V
350
300
700
600
T = 25°C
A
250
200
150
100
500
400
300
200
V
DD
= 2.5 V
T = 125°C
5.0 V
A
7.5 V
25°C
50
0
100
0
-ꢁ55°C
-ꢁ10 -ꢁ8.0 -ꢁ6.0 -ꢁ4.0 -ꢁ2.0
0
0.2 4.0
6.0 8.0 10
-ꢁ10 -ꢁ8.0 -ꢁ6.0 -ꢁ4.0 -ꢁ2.0
0
0.2 4.0
6.0 8.0
10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 15. Comparison at 25°C, VDD = −ꢀVEE
Figure 14. VDD = 2.5 V, VEE = − 2.5 V
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7
NLHV4051, NLHV4052, NLHV4053
APPLICATIONS INFORMATION
Figure A illustrates use of the on−chip level converter
detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control
signal is used to directly control a 9 V analog signal.
peak. If voltage transients above V and/or below V are
DD EE
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
p−p
The digital control logic levels are determined by V
DD
and V . The V voltage is the logic high voltage; the V
SS
DD
SS
voltage is logic low. For the example, V = +5 V = logic
The absolute maximum potential difference between
DD
high at the control inputs; V = GND = 0 V = logic low.
V
and V is 18.0 V. Most parameters are specified up to
DD EE
SS
The maximum analog signal level is determined by V
15 V which is the recommended maximum difference
between V and V
DD
and V . The V
voltage determines the maximum
.
EE
EE
DD
DD
recommended peak above
V
.
SS
The
V
voltage
Balanced supplies are not required. However, V must
EE
SS
determines the maximum swing below V . For the
be greater than or equal to V . For example, V = +10 V,
SS
EE
DD
example, V
− V = 5 V maximum swing above V
;
V
= +5 V, and V – 3 V is acceptable. See the Table
SS EE
DD
SS
SS
V
− V = 5 V maximum swing below V . The example
below.
SS
EE
SS
shows a 4.5 V signal which allows a 1/2 volt margin at each
+5 V
-5 V
V
DD
V
SS
V
EE
+4.5 V
9 V
SWITCH
I/O
p-p
+5 V
9 V
ANALOG SIGNAL
COMMON
O/I
p-p
GND
NLHV4051
NLHV4052
NLHV4053
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
−4.5 V
0-TO-5 V DIGITAL
CONTROL SIGNALS
INHIBIT,
A, B, C
CIRCUITRY
Figure A. Application Example
V
DD
V
DD
D
D
D
X
X
X
X
ANALOG
I/O
COMMON
O/I
D
V
EE
V
EE
Figure B. External Germanium or Schottky Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
Logic High/Logic Low
In Volts
V
V
V
EE
In Volts
Maximum Analog Signal Range
In Volts
DD
SS
In Volts
In Volts
+8
0
0
–8
+8/0
+5/0
+8 to –8 = 16 V
p–p
+5
–12
0
+5 to –12 = 17 V
p–p
+5
0
+5/0
+5 to 0 = 5 V
p–p
+5
0
–5
+5/0
+5 to –5 = 10 V
+10 to –5 = 15 V
p–p
+10
+5
–5
+10/ +5
p–p
www.onsemi.com
8
NLHV4051, NLHV4052, NLHV4053
ORDERING INFORMATION
†
Device
Package
Shipping
NLHV4051DR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
NLHV4051DTR2G
TSSOP−16
(Pb−Free)
NLHV4052DR2G
NLHV4052DTR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−16
(Pb−Free)
NLHV4053DR2G
(In Development)
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
NLHV4053DTR2G
(In Development)
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
9
NLHV4051, NLHV4052, NLHV4053
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
16X KREF
NOTES:
ꢂꢀ1.
M
S
S
0.10 (0.004)
T
U
V
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
U
0.15 (0.006) T
ꢂꢀ2.
ꢂꢀ3.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A DOES NOT INCLUDE MOLD FLASH.
K
K1
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
ꢂꢀ4.
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
2X L/2
J1
SECTION N−N
B
−U−
ꢂꢀ5.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
L
J
PIN 1
IDENT.
ꢂꢀ6.
REFERENCE ONLY.
ꢂꢀ7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
TERMINAL NUMBERS ARE SHOWN FOR
N
8
0.25 (0.010)
1
M
S
0.15 (0.006) T
U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
N
−V−
A
B
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
NLHV4051, NLHV4052, NLHV4053
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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◊
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