NLSF302 [ONSEMI]
Quad 2−Input NOR Gate; 四2输入或非门
| 型号： | NLSF302 |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2−Input NOR Gate |
| 文件： | 总4页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSF302
Quad 2−Input NOR Gate
The NLSF302 is an advanced high speed CMOS 2−input NOR gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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Features
1
• High Speed: t = 3.6 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
CC
A
QFN−16
MN SUFFIX
CASE 485G
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
MARKING DIAGRAM
• Low Noise: V
= 0.8 V (Max)
OLP
• Function Compatible with Other Standard Logic Families
• QFN−16 Package
16
1
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
NLSF
302
Machine Model > 200 V
• Chip Complexity: 40 FETs or 10 Equivalent Gates
• Pb−Free Package is Available*
ALYW G
G
FUNCTION TABLE
NLSF302 = Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Inputs
Output
Y
A
B
L
L
H
H
L
H
L
H
L
L
L
(Note: Microdot may be in either location)
H
ORDERING INFORMATION
†
Device
Package
Shipping
NLSF302MNR2
QFN−16
3000/Tape & Reel
3000/Tape & Reel
NLSF302MNR2G QFN−16
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
May, 2006 − Rev. 4
NLSF302/D
NLSF302
16
15
14
13
B1
NC
Y2
A2
B4
NC
A4
Y3
12
11
10
9
1
16
NLSF302
MN Package
A1
B1
2
15
3
Y1
Y2
Y3
Y4
1
4
5
3
4
(Top View)
A2
B2
Y = A + B
7
8
A3
B3
9
5
6
7
8
10
12
A4
B4
13
Figure 1. LOGIC DIAGRAM
Figure 2. PIN ASSIGNMENT (QFN−16)
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
DC Supply Voltage
DC Input Voltage
V
CC
– 0.5 to + 7.0
– 0.5 to + 7.0
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
V
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
mA
mA
mA
mA
mW
°C
cuit. For proper operation, V and
in
I
20
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
25
50
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
DC Supply Current, V and GND Pins
I
CC
level (e.g., either GND or V ).
Power Dissipation in Still Air
Storage Temperature
P
D
450
CC
Unused outputs must be left open.
T
stg
– 65 to + 150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
2.0
0
Max
5.5
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
V
in
5.5
V
V
out
0
V
CC
V
Operating Temperature
Input Rise and Fall Time
T
−40
+85
°C
ns/V
A
V
V
= 3.3 V 0.3 V
=5.0 V 0.5 V
t , t
r f
0
0
100
20
CC
CC
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2
NLSF302
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Symbol
V
Min
Typ
Max
Min
Max
Parameter
Test Conditions
Unit
Minimum High−Level
Input Voltage
V
IH
2.0
3.0 to 5.5
1.50
1.50
V
V
x 0.7
V
x 0.7
CC
CC
Maximum Low−Level
Input Voltage
V
2.0
3.0 to 5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
V
OH
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
IL
IL
IL
I
OH
V
in
= V or V
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
Maximum Low−Level
Output Voltage
V
in
= V or V
V
OL
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
I
OL
= 50 mA
V
= V or V
in
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
Maximum Input Leakage
Current
V
= 5.5 V or GND
I
0 to 5.5
0.1
1.0
mA
mA
in
in
Maximum Quiescent
Supply Current
V
in
= V or GND
I
5.5
2.0
20.0
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
Maximum Propagation Delay,
Input A or B to Output Y
V
= 3.3 0.3 V C = 15 pF
t ,
PLH
5.6
8.1
7.9
11.4
1.0
1.0
9.5
13.0
ns
CC
L
L
C = 50 pF
t
PHL
V
= 5.0 0.5 V C = 15 pF
3.6
5.1
5.5
7.5
1.0
1.0
6.5
8.5
CC
L
L
C = 50 pF
Maximum Input Capacitance
C
4
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
15
Power Dissipation Capacitance (Note 1)
C
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC(OPR
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
in
.
D
PD
CC
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Characteristic
Symbol
Unit
V
Quiet Output Maximum Dynamic V
V
OLP
0.8
− 0.8
3.5
OL
Quiet Output Minimum Dynamic V
V
OLV
− 0.3
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
V
ILD
1.5
V
TEST POINT
A or B
V
CC
50%
OUTPUT
GND
INPUT
DEVICE
UNDER
TEST
t
t
PHL
PLH
C *
L
50% V
Y
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
Figure 5. Input Equivalent Circuit
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3
NLSF302
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
E
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
TOP VIEW
A3
b
0.20 REF
0.18
0.15
C
0.30
D
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
0.10
0.08
C
C
E2 1.65
1.85
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
C
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
E2
e
K
16X
12
1
16
13
16X b
0.10 C A
B
BOTTOM VIEW
0.05
C
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NLSF302/D
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