NLSF3T125MNR2G [ONSEMI]
Quad Bus Buffer with 3-state Control Inputs;
| 型号： | NLSF3T125MNR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad Bus Buffer with 3-state Control Inputs 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSF3T125
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
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The NLSF3T125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The T125 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T125 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
1
QFN−16
CASE 485G
MARKING DIAGRAM
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
NLSF3
T125
ALYWG
G
NLSF3T125 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• High Speed: t = 3.8 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C
CC
A
(Note: Microdot may be in either location)
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
ORDERING INFORMATION
• Designed for 2.0 V to 5.5 V Operating Range
†
Device
Package
Shipping
• Low Noise: V
= 0.8 V (Max)
OLP
NLSF3T125MNR2G QFN−16 3000/Tape & Reel
(Pb−Free)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
FUNCTION TABLE
NLSF3T125
Inputs
Output
A
H
L
OE
L
Y
H
L
L
X
H
Z
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 5
NLSF3T125/D
NLSF3T125
Active−Low Output Enables
16
15
1
5
A1
Y1
OE1
4
3
A2
Y2
Y3
OE2
7
8
A3
9
OE3
10
12
13
A4
Y4
OE4
Figure 1. Logic Diagram
A1 OE1 V
OE4
13
CC
Exposed Pad (EP)
16
15
14
Y1
NC
A4
11 NC
1
2
3
12
OE2
A2
Y4
10
9
OE3
4
5
6
7
8
Y2 GND Y3
A3
Figure 2. QFN − 16 Pinout (Top View)
MAXIMUM RATINGS
Symbol
Parameter
Value
Units
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
–0.5 to +7.0
V
V
V
CC
V
in
V
out
Output in 3−State
–0.5 to +7.0
High or Low State
–0.5 to V + 0.5
CC
cuit. For proper operation, V and
in
I
IK
Input Diode Current
−20
20
mA
mA
mA
mA
mW
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
I
Output Diode Current (V
< GND; V
> V )
CC
OK
OUT
OUT
Unused inputs must always be
tied to an appropriate logic voltage
I
DC Output Current, per Pin
25
out
CC
level (e.g., either GND or V ).
CC
I
DC Supply Current, V and GND Pins
75
CC
Unused outputs must be left open.
P
D
Power Dissipation in Still Air
QFN Packages
500
T
stg
Storage Temperature
–65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
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2
NLSF3T125
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Units
V
CC
DC Supply Voltage
DC Input Voltage
V
V
V
V
in
5.5
V
out
DC Output Voltage
Output in 3−State
High or Low State
0
0
5.5
V
CC
T
Operating Temperature
Input Rise and Fall Time
−40
+85
°C
A
t , t
r
ns/V
f
V
= 5.0 V 0.5 V
0
20
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
3 85°C
T 3 125°C
A
V
CC
Symbol
(V)
Min
Typ
Max
Min
Max
Min
Max
Parameter
Test Conditions
Units
V
Minimum
High−Level
Input Voltage
2.3 V 0.3 V
3.3 V 0.3 V
5.0 V 0.5 V
0.5 V
0.4 V
0.5 V
0.4 V
0.5 V
0.4 V
V
V
V
IH
CC
CC
CC
CC
CC
CC
CC
CC
CC
0.44 V
0.44 V
0.44 V
V
Maximum
Low−Level
Input Voltage
2.3 V 0.3 V
3.3 V 0.3 V
5.0 V 0.5 V
0.3 V
0.18 V
0.18 V
0.3 V
0.18 V
0.18 V
0.3 V
CC
IL
CC
CC
CC
CC
CC
CC
0.18 V
0.18 V
CC
CC
V
OH
Minimum
V
V
OH
@ I , 50 mA 2.0
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
OL
IN
OL
High−Level
Output Voltage
= V or V
3.0
4.5
IH
IL
I
= −50 mA
V
IN
= V or V
IH IL
V
= V or V
IH
IN
OH
OH
OH
IL
I
I
I
= −2.0 mA
= −4.0 mA
= −8.0 mA
2.0
3.0
4.5
1.82
2.58
3.94
1.72
2.48
3.80
1.60
2.34
3.66
V
OL
Maximum
V
V
OL
@ I , 50 mA 2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
IN
OL
Low−Level
= V or V
3.0
4.5
IH
IL
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
OL
IH
IL
I
I
I
= 2.0 mA
= 4.0 mA
= 8.0 mA
2.0
3.0
4.5
0.36
0.36
0.36
0.44
0.44
0.44
0.52
0.52
0.52
I
Maximum
Input Leakage
Current
V
= 5.5 V or
0
to
0.1
1.0
1.0
mA
mA
mA
mA
IN
IN
GND
5.5
I
Maximum
V
= V or GND 5.5
2.0
20
40
CC
IN CC
Quiescent
Supply Current
I
Quiescent
Supply
Current
Input: V = 3.4 V
5.5
5.5
1.35
0.25
1.50
2.5
1.65
2.5
CCT
IN
I
Maximum
3−State
Leakage
Current
V
V
= V or V
IH IL
OZ
IN
= V or GN
OUT
D
CC
I
Output
Leakage
Current
V
OUT
= 5.5 V
0.0
0.5
5.0
10
mA
OPD
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3
NLSF3T125
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T
3 85°C
Max
T 3 125°C
A
A
Min
Typ
Max
Min
Min
Max
Symbol
Parameter
Test Conditions
= 2.3 0.3 V C = 15 pF
Units
ns
t
,
Maximum Propagation
Delay, A to Y
V
V
1.0
14.5 16.9
1.0
18.1
1.0
19.2
PLH
CC
L
t
PHL
= 3.3 0.3 V C = 15 pF
1.0
1.0
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
12.0
16.0
ns
CC
L
C = 50 pF
L
V
CC
= 5.0 0.5 V C = 15 pF
1.0
1.0
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
8.5
10.5
L
C = 50 pF
L
Maximum Output
Enable TIme, OE to Y
V
V
= 2.3 0.3 V C = 15 pF
1.0
14.8 16.2
1.0
17.4
1.0
19.3
ns
ns
CC
L
t
t
,
PZL
= 3.3 0.3 V C = 15 pF
1.0
1.0
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
11.5
15.0
CC
L
t
PZH
R = 1.0 kW
C = 50 pF
L
L
V
= 5.0 0.5 V C = 15 pF
1.0
1.0
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
1.0
1.0
7.5
9.5
CC
L
R = 1.0 kW
C = 50 pF
L
L
,
Maximum Output
V
V
= 2.3 0.3 V C = 15 pF
1.0
1.0
15.4 18.0
1.0
1.0
19.8
15.0
1.0
1.0
22.0
18.0
ns
ns
PLZ
CC
L
t
Disable Time, OE to Y
PHZ
= 3.3 0.3 V C = 50 pF
9.5
13.2
8.8
1.5
1.0
10
CC
L
R = 1.0 kW
L
V
CC
= 5.0 0.5 V C = 50 pF
1.0
6.1
1.0
10.0
1.5
1.0
10
1.0
12.0
2.0
1.5
10
ns
ns
L
R = 1.0 kW
L
t
,
Output−to−Output Skew
V
= 3.3 0.3 V C = 50 pF
OSLH
CC L
t
(Note 1)
OSHL
V
CC
= 5.0 0.5 V C = 50 pF
L
(Note 1)
C
Maximum Input
Capacitance
4
6
pF
pF
in
C
Maximum Three−State
Output Capacitance
(Output in High Impedance
State)
out
Typical @ 25°C, V = 5.0V
CC
C
Power Dissipation Capacitance (Note 2)
= |t − t
15
pF
PD
1. Parameter guaranteed by design. t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /4 (per buffer). C is used to determine the
CC(OPR
CC
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
in
.
D
PD
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
0.8
Symbol
Characteristic
Units
V
Quiet Output Maximum Dynamic V
V
V
V
V
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
−0.8
3.5
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
ILD
1.5
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4
NLSF3T125
SWITCHING WAVEFORMS
3.0V
GND
OE
1.5V
3.0V
1.5V
t
t
t
PZL
PLZ
A
Y
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
1.5V
t
Y
V
OH
V
V
+ 0.3V
OL
1.5V
PZH
PHZ
V
OL
- 0.3V
OH
1.5V
Y
HIGH
IMPEDANCE
Figure 3.
Figure 4.
TEST POINT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
OUTPUT
PZL.
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE G
1
DATE 08 OCT 2021
SCALE 2:1
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04795D
QFN16 3X3, 0.5P
PAGE 1 OF 1
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