NLSX4401DFT2G [ONSEMI]
1-Bit 20 Mb/s Dual-SupplyLevel Translator;
| 型号： | NLSX4401DFT2G |
| 厂家： | 
ONSEMI |
| 描述： | 1-Bit 20 Mb/s Dual-SupplyLevel Translator |
| 文件： | 总15页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSX4401DFT2G
1-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4401DFT2G is a 1−bit configurable dual−supply
bidirectional auto sensing translator that does not require a
directional control pin. The I/O V and I/O V ports are designed to
CC
L
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track two different power supply rails, V
and V respectively.
CC
L
Both the V and V supply rails are configurable from 1.65 V to
CC
L
5.5 V. This allows voltage logic signals on the V side to be
translated into lower, higher or equal value voltage logic signals on
L
MARKING
DIAGRAM
the V side, and vice−versa.
CC
The NLSX4401DFT2G translator has integrated 10 kW pull−up
6
resistors on the I/O lines. The integrated pull−up resistors are used to
SC−88
2.10 x 2.0
CASE 419B
XXXMG
pull up the I/O lines to either V or V . The NLSX4401 is an
L
CC
G
2
excellent match for open−drain applications such as the I C
communication bus.
1
1
XXX = Specific Device Code
M
G
= Date Code*
= Pb−Free Package
Features
• V can be Less than, Greater than or Equal to V
L
CC
(Note: Microdot may be in either location)
• Wide V Operating Range: 1.65 V to 5.5 V
CC
*Date Code orientation and/or position may vary
dependingupon manufacturing location.
Wide V Operating Range: 1.65 V to 5.5 V
L
• High Speed with 24 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
LOGIC DIAGRAM
• Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V
• Non−preferential Powerup Sequencing
V
V
CC
GND
L
EN
• Partial Power−Off Protection − I/Os at High Impedance with Either
Supply at 0 V
• Integrated 10 kW Pull−up Resistors
• Small Space Saving Packages:
I/O V
I/O V
CC
L
SC−88/SC70−6/SOT−363 Package
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
ORDERING INFORMATION
2
• I C, SMBus, PMBus
†
Device
NLSX4401DFT2G
Package
Shipping
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
SC−88
3000 / Tape
& Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 5000 V
©
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
September, 2018 − Rev. 0
NLSX4401/D
NLSX4401DFT2G
Figure 1. Block Diagram (1 I/O Line)
V
6
V
CC
L
1
2
EN
GND
5
4
3
I/O V
I/O V
L
CC
SC−88 / SC70−6 / SOT−363
(Top Through View)
Figure 2. Pinout Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
Supply Voltage
EN
L
Operating Mode
Hi−Z
V
V
CC
CC
L
V
V Supply Voltage
L
H
I/O Buses Connected
GND
EN
Ground
Output Enable, Referenced to V
L
I/O V
I/O Port, Referenced to V
CC
L
CC
L
I/O V
I/O Port, Referenced to V
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2
NLSX4401DFT2G
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
DC Supply Voltage
DC Supply Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
50
CC
L
V
V
I/O V
I/O V
V
−Referenced DC Input/Output Voltage
V
CC
CC
V −Referenced DC Input/Output Voltage
L
V
L
V
EN
Enable Control Pin DC Input Voltage
V
I
I
Short−Circuit Duration (I/O V and I/O V to GND)
Continuous
V < 0
I/O
mA
mA
°C
I/O_SC
I/OK
L
CC
Input/Output Clamping Current (I/O V and I/O V
)
CC
−50
L
T
STG
Storage Temperature
−65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.5
Max
5.5
5.5
5.5
5.5
5.5
Unit
V
V
CC
Positive DC Supply Voltage
Positive DC Supply Voltage
Enable Control Pin Voltage
I/O Pin Voltage (Side referred to V
V
L
1.5
V
V
EN
GND
GND
GND
V
V
)
CC
V
IO_VCC
V
IO_VL
I/O Pin Voltage (Side referred to V )
V
L
Dt/DV
Input Transition Rise and Fall Rate
A− or B−Ports, Push−Pull Driving
Control Input
10
10
ns/V
T
A
Operating Temperature Range
−55
+125
°C
Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
RecommendedOperating Ranges limits may affect device reliability.
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3
NLSX4401DFT2G
DC ELECTRICAL CHARACTERISTICS (V = 1.65 V to 5.5 V and V = 1.65 V to 5.5 V, unless otherwise specified) (Note 1)
L
CC
−555C to +1255C
Min
V – 0.4
CC
Typ
Max
−
Symbol
Parameter
I/O V Input HIGH Voltage
Test Conditions (Note 2)
Unit
V
V
−
−
−
−
−
IHC
CC
V
V
I/O V Input LOW Voltage
−
0.15
−
V
ILC
CC
I/O VL Input HIGH Voltage
I/O VL Input LOW Voltage
V – 0.4
V
IHL
L
V
ILL
−
0.15
−
V
V
Control Pin Input HIGH Voltage
Control Pin Input LOW Voltage
0.65 * V
V
IH
L
V
V = 1.65 V to 1.95 V
−
−
−
−
0.25 * V
0.35 * V
V
IL
L
L
L
V = 2.3 V to 5.5 V
L
V
I/O VCC Output HIGH Voltage
I/O VCC Output LOW Voltage
I/O V source current = 20 mA
2/3 * V
−
−
−
−
−
−
V
V
OHC
CC
CC
V
I/O V sink current = 1 mA
0.4
−
OLC
CC
V
I/O V
I/O VL Output LOW Voltage
Supply Current
L
Output HIGH Voltage
I/O V source current = 20 mA
2/3 * V
−
V
OHL
L
L
V
I/O V sink current = 1 mA
0.4
V
OLL
L
I
V
CC
I/O V and I/O V unconnected, V = V
L
−
−
−
0.5
−
−
3.0
−1.0
1.0
mA
QVCC
CC
L
EN
CC
CC
V = 5.5 V, V = 0 V
L
V = 0 V, V = 5.5 V
L
I
VL Supply Current
I/O V and I/O V unconnected, V = V
L
−
−
−
0.3
−
−
3.0
1.0
−1.0
mA
QVL
CC
L
EN
V = 5.5 V, V = 0 V
L
L
CC
V
V
= 0 V,
= 5.5 V
CC
I
V
Tristate Output Mode
I/O V and I/O V unconnected, V = GND
−
−
0.1
0.1
1.5
1.5
mA
mA
TS−VCC
CC
CC
L
EN
I
V Tristate Output Mode Supply
L
I/O V and I/O V unconnected, V = GND
CC L EN
TS−VL
Current
I
Enable Pin Input Leakage Current
I/O Power-Off Leakage Current
−
−
−
−
−
−
1.0
1.0
1.0
1.0
mA
mA
I
I
I/O V Port, V = 0 V, V = 0 to 5.5 V
CC CC L
OFF
I/O VL Port, VCC = 0 to 5.5 V, V = 0 V
−
L
I
I/O Tristate Output Mode
Leakage Current
0.1
mA
kΩ
OZ
R
PU
Pull−Up Resistors
−
10
−
I/O V and V
L
C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performancemay not be indicated by the Electrical Characteristics if operated under different conditions.
1. Typical values are for V = +1.8 V, V = +3.3 V and T = +25°C.
L
CC
A
2. All units are production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
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4
NLSX4401DFT2G
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 1.65 V, V = 1.65 V
L
CC
t
I/O V Rise Time
9
32
20
30
13
16
15
269
300
2
ns
ns
RVCC
CC
t
I/O V Fall Time
11
20
10
7
FVCC
CC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
12
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
15
Mbps
V = 1.65 V, V = 5.5 V
L
CC
t
I/O V Rise Time
9
17
8
12
30
10
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
5
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
14
4
24
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
, t
Enable Time
66
250
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
20
Mbps
V = 1.8 V, V = 2.8 V
L
CC
t
I/O V Rise Time
11
10
12
5
18
15
15
8
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
7
10
12
100
300
2
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
1
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
20
Mbps
V = 2.5 V, V = 3.6 V
L
CC
t
I/O V Rise Time
8
12
ns
RVCC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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5
NLSX4401DFT2G
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 2.5 V, V = 3.6 V
L
CC
t
I/O V Fall Time
8
7
5
7
5
12
10
7
ns
ns
FVCC
CC
t
I/O V Rise Time
L
RVL
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
10
8
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
, t
Enable Time
74
225
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 2.8 V, V = 1.8 V
L
CC
t
I/O V Rise Time
13
7
20
10
13
15
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
8
ns
RVL
L
t
I/O V Fall Time
9
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
7
12
103
250
2
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 3.6 V, V = 2.5 V
L
CC
t
I/O V Rise Time
9
6
6
7
5
6
12
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
12
12
7
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
9
ns
CC CC
L
t
, t
Enable Time
77
250
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
V = 5.5 V, V = 1.65 V
L
CC
t
I/O V Rise Time
13
6
20
9
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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6
NLSX4401DFT2G
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 3 and 4, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 3 & 4)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 5.5 V, V = 1.65 V
L
CC
t
I/O V Rise Time
8
22
9
10
37
13
25
ns
ns
RVL
L
t
I/O V Fall Time
L
FVL
t
t
Propagation Delay (Driving I/O V , V to V )
CC
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
13
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
2
ns
PPSKEW
MDR
20
Mbps
V = 5.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
5
6
5
5
4
4
7
8
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
7
ns
RVL
L
t
I/O V Fall Time
8
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
ns
CC CC
L
t
, t
Enable Time
30
225
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
24
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
4. Limits over the operating temperature range are guaranteed by design.
5. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
V = 1.65 V, V = 1.65 V
Parameter
Test Conditions
Unit
L
CC
t
I/O V Rise Time
55
7
70
14
65
12
ns
ns
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
50
7
RVL
L
t
I/O V Fall Time
L
FVL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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7
NLSX4401DFT2G
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 1.65 V, V = 1.65 V
L
CC
t
t
Propagation Delay (Driving I/O V , V to V )
CC
20
19
34
34
ns
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
CC CC
L
t
, t
Enable Time
100
300
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 1.65 V, V = 5.5 V
L
CC
t
I/O V Rise Time
22
20
43
6
34
27
55
12
26
24
80
250
2
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
13
19
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 1.8 V, V = 3.3 V
L
CC
t
I/O V Rise Time
34
1
40
15
48
2
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
40
1
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
9
15
11
70
300
2
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
ns
CC CC
L
t
, t
Enable Time
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
7
Mbps
V = 5.5 V, V = 1.65 V
L
CC
t
I/O V Rise Time
44
1
52
2
ns
ns
ns
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
7
30
23
17
RVL
L
t
I/O V Fall Time
17
10
FVL
PDVL−VCC
L
t
Propagation Delay (Driving I/O V , V to V
)
CC
L
L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
www.onsemi.com
8
NLSX4401DFT2G
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (continued)
(I/O test circuit of Figures 5 and 6, C
= 15 pF, driver output impedance ≤ 50 W, R
= 1 MW)
LOAD
LOAD
−405C to +855C
(Notes 6 & 7)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Unit
V = 5.5 V, V = 1.65 V
L
CC
t
Propagation Delay (Driving I/O V , V to V )
12
24
100
300
2
ns
ns
PDVCC−VL
CC CC
L
t
, t
Enable Time
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
3
Mbps
V = 5.5 V, V = 5.5 V
L
CC
t
I/O V Rise Time
42
2
50
3
ns
ns
RVCC
CC
t
I/O V Fall Time
CC
FVCC
t
I/O V Rise Time
44
2
48
3
ns
RVL
L
t
I/O V Fall Time
ns
FVL
L
t
t
Propagation Delay (Driving I/O V , V to V )
CC
4
6
ns
PDVL−VCC
PDVCC−VL
L
L
Propagation Delay (Driving I/O V , V to V )
6
9
ns
CC CC
L
t
, t
Enable Time
60
225
2
ns
PZL PZH
t
, t
Disable Time
ns
PLZ PHZ
t
Part−to−Part Skew
Maximum Data Rate
ns
PPSKEW
MDR
7
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product perfor-
mance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Typical values are for the specified V and V at T = +25°C. All units are production tested at T = +25°C.
L
CC
A
A
7. Limits over the operating temperature range are guaranteed by design.
8. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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9
NLSX4401DFT2G
TEST SETUP
NLSX4401
NLSX4401
V
L
V
CC
V
L
V
CC
EN
EN
I/O V
I/O V
L
I/O V
L
I/O V
CC
CC
Source
C
LOAD
C
LOAD
Source
R
LOAD
R
LOAD
Figure 3. Rail−to−Rail Driving I/O VL
Figure 4. Rail−to−Rail Driving I/O VCC
NLSX4401
NLSX4401
V
L
V
L
V
CC
V
CC
EN
EN
I/O V
CC
I/O V
L
I/O V
CC
V
CC
C
LOAD
C
LOAD
R
LOAD
R
LOAD
Figure 5. Open−Drain Driving I/O VL
Figure 6. Open−Drain Driving I/O VCC
t
v
I/O V
t
v 3 ns
RISE/FALL
I/O V
CC
RISE/FALL
L
3 ns
90%
50%
10%
90%
50%
10%
t
L
t
t
t
PD_VCC−VL
PD_VL−VCC
PD_VL−VCC
PD_VCC−VL
I/O V
I/O V
CC
90%
50%
10%
90%
10%
90%
10%
90%
50%
10%
t
t
R−VCC
t
t
R−VL
F−VCC
F−VL
Figure 7. Definition of Timing Specification Parameters
www.onsemi.com
10
NLSX4401DFT2G
V
CC
2xV
CC
OPEN
R
1
DUT
EN
C
L
R
L
Test
Switch
t
t
, t
Open
PZH PHZ
, t
2 x V
CC
PZL PLZ
C = 15 pF or equivalent (Includes jig and probe capacitance)
L
R = R = 50 kW or equivalent
L
1
Figure 8. Test Circuit for Enable/Disable Time Measurement
V
L
50%
EN
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
Output
10%
90%
V
V
OL
t
t
PHZ
PZH
OH
50%
Output
HIGH
IMPEDANCE
Figure 9. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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11
NLSX4401DFT2G
APPLICATIONS INFORMATION
Level Translator Architecture
impedance of the device that is connected to the translator.
The timing parameters listed in the data sheet assume that
the output impedance of the drivers connected to the
translator is less than 50 kW.
The NLSX4401 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, V and V , which set the logic levels on
L
CC
Enable Input (EN)
the input and output sides of the translator. When used to
transfer data from the I/O V to the I/O V ports, input
The NLSX4401 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O V and I/O V pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
L
CC
signals referenced to the V supply are translated to output
L
signals with a logic level matched to V . In a similar
CC
CC
L
manner, the I/O V to I/O V translation shifts input
CC
L
signals with a logic level compatible to V to an output
CC
signal matched to V .
L
is referenced to the V supply and has Overvoltage
Tolerant (OVT) protection.
L
The NLSX4401 consists of a bi−directional channels that
independently determines the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising input signals. In addition, the
one shots decrease the rise time of the output signal for
low−to−high transitions.
Each input/output channel has an internal 10 kW
pull−up. The magnitude of the pull−up resistors can be
reduced by connecting external resistors in parallel to the
internal 10 kW resistors.
Power Supply Guidelines
During normal operation, supply voltage V can be
greater than, less than or equal to V . The sequencing of
the power supplies will not damage the device during the
power up operation.
L
CC
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the V
and V
power
CCA
CCB
supply pins. Ceramic capacitors are a good design choice
to filter and bypass any noise signals on the voltage lines
to the ground plane of the PCB. The noise immunity will
be maximized by placing the capacitors as close as possible
to the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (t ) and fall (t ) timing parameters of the open
R
F
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (t / t ),
PHL PLH
skew (t
) and maximum data rate depend on the
PSKEW
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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