NLSX5014_18_技术文档

NLSX5014

4-Bit 100 Mb/s Configurable

Dual-Supply Level

Translator

The NLSX5014 is a 4-bit configurable dual-supply autosensing

bidirectional level translator that does not require a direction control

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pin. The I/O V - and I/O V -ports are designed to track two

CC

L

different power supply rails, V and V respectively. Both the V

CC

L

CC

MARKING

DIAGRAMS

and the V supply rails are configurable from 0.9 V to 4.5 V. This

L

allows a logic signal on the V side to be translated to either a higher

L

or a lower logic signal voltage on the V side, and vice-versa.

UQFN12

MU SUFFIX

CASE 523AE

CC

AAMG

The NLSX5014 offers the feature that the values of the V and

CC

G

1

V

L

supplies are independent. Design flexibility is maximized

because V can be set to a value either greater than or less than the

L

M

G

= Date Code

= Pb−Free Package

V

CC

supply. In contrast, the majority of competitive auto sense

translators have a restriction that the value of the V supply must be

L

(Note: Microdot may be in either location)

equal to less than (V - 0.4) V.

CC

The NLSX5014 has high output current capability, which allows the

14

translator to drive high capacitive loads such as most high frequency

SOIC−14

D SUFFIX

CASE 751A

NLSX5014G

AWLYWW

14

EMI filters. Another feature of the NLSX5014 is that each I/O_V and

Ln

1

I/O_V

channel can function as either an input or an output.

CCn

1

An Output Enable (EN) input is available to reduce the power

consumption. The EN pin can be used to disable both I/O ports by

putting them in 3-state which significantly reduces the supply current

14

NLSX

5014

ALYWG

G

TSSOP−14

DT SUFFIX

CASE 948G

from both V and V . The EN signal is referenced to the V supply.

CC

L

14

1

Features

1

• Wide V , V Operating Range: 0.9 V to 4.5 V

CC

L

• V and V are independent

A

=

Assembly Location

Wafer Lot

L

CC

WL, L

YY, Y

WW, W

G or G

− V may be greater than, equal to, or less than V

L

CC

Year

Work Week

• High 100 pF Capacitive Drive Capability

• High−Speed with 140 Mb/s Guaranteed Date Rate

= Pb−Free Package

(Note: Microdot may be in either location)

for V , V > 1.8 V

CC

L

• Low Bit−to−Bit Skew

• Overvoltage Tolerant Enable and I/O Pins

• Non−preferential Powerup Sequencing

• Power−Off Protection

• Small packaging: 1.7 mm x 2.0 mm UQFN12, SOIC14, TSSOP14

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

ORDERING INFORMATION

†

Device

Package

Shipping

NLSX5014MUTAG

NLSX5014DR2G

NLSX5014DTR2G

UQFN12 3000/Tape & Reel

(Pb−Free)

SO−14

2500/Tape & Reel

(Pb−Free)

Typical Applications

TSSOP14 2500/Tape & Reel

(Pb−Free)

• Mobile Phones, PDAs, Other Portable Devices

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Important Information

• ESD Protection for All Pins:

♦ HBM (Human Body Model) > 7000 V

©

Semiconductor Components Industries, LLC, 2014

1

Publication Order Number:

April, 2018 − Rev. 8

NLSX5014/D

NLSX5014

P

V

L

V

CC

One−Shot

R1

+1.8V

+3.6V

1k

N

V

L

V

CC

One−Shot

NLSX5014

+1.8 V System

+3.6 V System

I/O V

CC

L

P

One−Shot

I/O V 1 I/O V

1

I/O1

I/On

L

CC

I/On

GND OE

I/O V n I/O V

n

R2

1k

L

CC

EN

GND

N

One−Shot

Figure 1. Typical Application Circuit

Figure 2. Simplified Functional Diagram (1 I/O Line)

2.5 V

3.0 V

1.8 V

V

L

V

CC

V

L

V

CC

mC

Temperature

Sensor

Temperature

Sensor

NLSX5014

CE

I/O V 1 I/O V

1

2

3

CE

I/O V 1 I/O V

1

2

3

CE

L

CC

L

CC

I/O V 2 I/O V

SCK

SDO

SCK

SDI

SDO

SCK

SDO

SCK

SDI

SDO

L

I/O V 3 I/O V

L

SDI

I/O V 4 I/O V

4

SDI

I/O V 4 I/O V

4

L

CC

L

CC

ANO

EN

GND

ANO

EN

GND

Figure 3. Application Example for V_L< V_CC

Figure 4. Application Example for V_L> V_CC

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2

NLSX5014

V

1

2

3

4

5

6

7

14

13

12

11

10

9

EN

V

L

I/O V 1

CC

L

EN

12

V

I/O V 2

I/O V

1

2

V

L

1

2

3

4

5

11

10

9

L

CC

I/O V 1

I/O V

1

L

CC

I/O V 3

CC

L

I/O V 2

I/O V

2

3

L

CC

I/O V 4

I/O V

NC

3

CC

L

I/O V 3

8

L

CC

NC

6

7

I/O V

4

CC

I/O V 4

L

I/O V

4

CC

8

GND

UQFN12

(Top View)

TSSOP/SOIC

(Top View)

Figure 1. Pin Assignments

V

L

V

CC

GND

EN

I/O V 1

CC

L

I/O V 2

I/O V

2

3

L

CC

I/O V 3

L

CC

I/O V 4

CC

L

Figure 2. Logic Diagram

PIN ASSIGNMENT

Pins

FUNCTION TABLE

Description

EN

L

Operating Mode

Hi−Z

V

CC

L

V

CC

Input Voltage

V

V Input Voltage

L

H

I/O Buses Connected

GND

EN

Ground

Output Enable

I/O V

n

I/O Port, Referenced to V

CC

L

I/O V n

I/O Port, Referenced to V

L

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3

NLSX5014

MAXIMUM RATINGS

Symbol

Parameter

Value

−0.5 to +5.5

−50

Condition

Unit

V

High−side DC Supply Voltage

Low−side DC Supply Voltage

−Referenced DC Input/Output Voltage

CC

L

V

I/O V

V

CC

V

CC

V −Referenced DC Input/Output Voltage

L

V

L

V

Enable Control Pin DC Input Voltage

DC Input Diode Current

V

I

V < GND

mA

°C

IK

I

DC Output Diode Current

−50

V < GND

O

OK

CC

L

DC Supply Current Through V

$100

CC

DC Supply Current Through V

$100

L

DC Ground Current Through Ground Pin

Storage Temperature

$100

GND

T

STG

−65 to +150

ESD Rating

Machine Model

Human Body Model

Charged Device Model

LU Pass

400

7000

2000

100

V

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

High−side Positive DC Supply Voltage

Min

0.9

Max

4.5

Unit

V

CC

V

L

Low−side Positive DC Supply Voltage

Enable Control Pin Voltage

0.9

V

I

GND

V

IO

Bus Input/Output Voltage

I/O V

GND

4.5

V

CC

L

I/O V

T

Operating Temperature Range

−55

+125

10

°C

A

Dt/DV

Input Transition Rise or Rate

0

ns

V , V from 30% to 70% of V ; V = 3.3 V $ 0.3 V

I

IO

CC CC

Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the

RecommendedOperating Ranges limits may affect device reliability.

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4

NLSX5014

DC ELECTRICAL CHARACTERISTICS

−405C to +855C

−555C to +1255C

Typ

Test Conditions

(Note 1)

V

(V)

V (V)

(Note 3)

CC

L

(Note 4)

(Note 2)

Min

Max

Min

Max

Symbol

Parameter

I/O V Input HIGH Voltage

Unit

V

IHC

0.9 – 4.5 0.9 – 4.5

1.2 – 4.5 1.2 – 4.5

2/3 *

CC

−

2/3 *

CC

−

V

CC

V

I/O V Input LOW Voltage

−

1/3 *

−

2/3 * V

−

1/3 *

V

ILC

IHL

CC

V

CC

V

CC

V

I/O V Input HIGH Voltage

2/3 *

−

1/3 * V

−

L

V

L

V

ILL

I/O V Input LOW Voltage

−

1/3 *

V

L

V

L

V

IH

Control Pin Input HIGH Volt-

age

T = +25°C

2/3 *

−

2/3 * V

−

V

A

L

V

L

V

IL

Control Pin Input LOW Volt-

age

T = +25°C

A

−

1/3 *

1/3 * V

−

V

L

V

L

V

IH

Control Pin Input HIGH Volt-

age

T = +25°C

A

V

< 1.2 V < 1.2

V

L

−

V

L

V

CC

L

V

IL

Control Pin Input LOW Volt-

age

T = +25°C

A

< 1.2 V < 1.2

−

0

−

0

V

CC

L

V

OHC

I/O V Output HIGH Volt-

I/O V source

0.9 – 4.5 0.9 – 4.5

0.9 *

−

V

CC

age

current = 20 mA

V

CC

V

CC

V

I/O V Output LOW Voltage

I/O V sink

−

0.2

−

0.2

−

V

OLC

OHL

CC

current = 20 mA

V

I/O V Output HIGH Voltage

I/O V source

0.9 *

0.9 * V

V

L

current = 20 mA

V

L

V

OLL

I/O V Output LOW Voltage

I/O V sink current 0.9 – 4.5 0.9 – 4.5

−

0.2

1

−

0.2

2.5

V

L

= 20 mA

I

V

CC

Supply Current

EN = V , I = 0 A, 0.9 – 4.5 0.9 – 4.5

−

mA

QVCC

L O

(I/O V = 0 V or

CC

V

, I/O V = float)

CC

L

or

(I/O V = float, I/O

CC

I

V Supply Current

L

0.9 – 4.5 0.9 – 4.5

−

1

−

2.5

1.5

mA

QVL

V = 0 V or V )

L

I

V

Tristate Output Mode

T = +25°C,

0.5

TS−VCC

CC

A

Supply Current

EN = 0 V

(I/O V = 0 V or

CC

V

, I/O V = float)

CC

L

I

V Tristate Output Mode

0.9 – 4.5 0.9 – 4.5

−

0.5

1

−

1.5

mA

or

TS−VL

L

Supply Current

(I/O V = float, I/O

CC

V = 0 V or V )

L

I

I/O Tristate Output Mode

Leakage Current

T = +25°C,

0.9 – 4.5 0.9 – 4.5

OZ

A

EN = 0V

I

Control Pin Input Current

T = +25°C

A

−

1

−

1

1.5

mA

I

Power Off Leakage Current

I/O V = 0 to 4.5V,

0

OFF

CC

I/O V = 0 to 4.5 V 0.9 – 4.5

1

L

0

0.9 – 4.5

1

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performancemay not be indicated by the Electrical Characteristics if operated under different conditions.

1. Normal test conditions are V = 0 V, C

≤ 15 pF and C

≤ 15 pF, unless otherwise specified.

CC

I

IOVCC

IOVL

2. V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

CC

3. V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

L

4. Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C. All units are production tested at T = +25°C. Limits over the operating

CC

L

A

temperaturerange are guaranteed by design.

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5

NLSX5014

TIMING CHARACTERISTICS

−555C to +1255C

Typ

Test Conditions

V

(V)

V (V)

CC

L

(Note 8)

(Note 5)

(Note 6)

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

(Note 7)

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

Min

−

Max

8.5

3.5

8.5

3.5

8.5

3.5

8.5

3.5

Symbol

Parameter

I/O V Rise Time

Unit

t

C

= 15 pF

−

nS

R−VCC

CC

IOVCC

−

t

I/O V Fall Time

C

IOVCC

−

nS

W

F−VCC

CC

−

t

I/O V Rise Time

C

−

R−VL

L

IOVL

−

t

I/O V Fall Time

C

−

F−VL

L

IOVL

−

Z

I/O V One−Shot

(Note 9)

0.9

1.8

4.5

−

37

20

6.0

−

OVCC

CC

Output Impedance

Z

OVL

I/O V One−Shot Out-

(Note 9)

0.9

1.8

4.5

0.9 – 4.5

−

37

20

6.0

−

W

L

put Impedance

t

Propagation Delay

C

= 15 pF

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

0.9 – 4.5

−

35

10

35

10

37

11

nS

PD_VL−VCC

IOVCC

(Driving I/O V

)

CC

= 30 pF

= 50 pF

= 100 pF

= 15 pF

= 30 pF

= 50 pF

= 100 pF

C

IOVCC

40

13

35

10

35

10

37

11

t

Propagation Delay

C

nS

PD_VCC−VL

IOVL

(Driving I/O V )

L

C

40

13

0.15

IOVL

t

SK

Channel−to−Channel

Skew

C

IOVCC

= 15 pF, C = 15 pF

IOVL

nS

(Note 9)

I

Input Driver Maximum

Peak Current

EN = V ;

0.9 – 4.5

−

5.0

mA

IN_PEAK

L

I/O_V = 1 MHz Square Wave,

CC

Amplitude = V , or

CC

I/O_V = 1 MHz Square Wave,

L

Amplitude = V (Note 9)

L

5. Normal test conditions are V = 0 V, C

≤ 15 pF and C

≤ 15 pF, unless otherwise specified.

CC

I

IOVCC

IOVL

6. V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

CC

7. V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

L

8. Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C. All units are production tested at T = +25°C. Limits over the operating

CC

L

A

temperaturerange are guaranteed by design.

9. Guaranteed by design.

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6

NLSX5014

TIMING CHARACTERISTICS (continued)

−555C to +1255C

Typ

Test Conditions

V

(V)

V (V)

(Note 12)

CC

L

(Note 13)

(Note 10)

(Note 11)

Min

Max

Symbol

Parameter

I/O_V Output Enable Time

Unit

t

C

= 15 pF,

IOVCC

0.9 – 4.5

−

160

nS

EN−VCC

CC

PZH

I/O_V = V

L

t

C

= 15 pF,

IOVCC

0.9 – 4.5

−

130

160

130

210

175

210

175

PZL

I/O_V = 0 V

L

t

I/O_V Output Enable Time

t

C = 15 pF,

IOVL

I/O_V = V

nS

EN−VL

L

PZH

CC

t

C

= 15 pF,

PZL

IOVL

I/O_V = 0 V

CC

t

I/O_V Output Disable Time

t

C = 15 pF,

IOVCC

DIS−VCC

CC

PHZ

I/O_V = V

L

t

C

= 15 pF,

IOVCC

PLZ

PHZ

I/O_V = 0 V

L

t

I/O_V Output Disable Time

t

C = 15 pF,

IOVL

I/O_V = V

nS

DIS−VL

L

CC

t

C

= 15 pF,

PLZ

IOVL

I/O_V = 0 V

CC

MDR

Maximum Data Rate

C

= 15 pF

= 30 pF

= 50 pF

= 100 pF

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

0.9 – 4.5

1.8 – 4.5

1.0 – 4.5

1.8 – 4.5

1.2 – 4.5

1.8 – 4.5

50

140

40

−

mbps

IO

120

30

100

20

C

IO

60

10.Normal test conditions are V = 0 V, C

≤ 15 pF and C

≤ 15 pF, unless otherwise specified.

CC

I

IOVCC

IOVL

11. V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

CC

12.V is the supply voltage associated with the I/O V port, and V ranges from +0.9 V to 4.5 V under normal operating conditions.

L

13.Typical values are for V = +2.8 V, V = +1.8 V and T = +25°C. All units are production tested at T = +25°C. Limits over the operating

CC

L

A

temperaturerange are guaranteed by design.

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7

NLSX5014

DYNAMIC POWER CONSUMPTION (T = +25°C)

A

Symbol

Parameter

Test Conditions

V

CC

(V)

V (V)

L

Typ

Unit

(Note 14)

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

(Note 15)

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

(Note 16)

C

V = Input port,

CC

C = 0, f = 1 MHz,

Load

39

20

17

14

13

14

13

19

37

30

29

30

29

19

29

30

29

35

21

18

14

13

14

13

30

pF

PD_VL

L

V

= Output Port EN = V (outputs enabled)

L

V

= Input port,

C

Load

= 0, f = 1 MHz,

pF

CC

L

V = Output Port EN = V (outputs enabled)

L

C

V = Input port,

CC

C = 0, f = 1 MHz,

Load

PD_VCC

L

V

= Output Port EN = V (outputs enabled)

L

V

= Input port,

C

Load

= 0, f = 1 MHz,

CC

L

V = Output Port EN = V (outputs enabled)

L

14.V

is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

CC

15.V is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

L

16.Typical values are at T = +25°C.

A

17.C

and C

are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the

PD VL

PD VCC

V and V power supplies, respectively. I = I (dynamic) + I (static) ≈ I (operating) ≈ C x V x f x N

L

+ I

where I = I

CC CC_VCC

CC

and N

CC

PD

CC

IN

SW

= total number of outputs switching.

CC VL

SW

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8

NLSX5014

STATIC POWER CONSUMPTION (T = +25°C)

A

Symbol

Parameter

Test Conditions

V

CC

(V)

V (V)

L

Typ

Unit

(Note 18)

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

0.9

1.5

1.8

2.5

2.8

4.5

(Note 19)

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

4.5

1.8

1.5

1.8

2.8

2.5

1.8

0.9

(Note 20)

C

V = Input port,

CC

C = 0, f = 1 MHz,

Load

0.01

pF

PD_VL

L

V

= Output Port EN = GND (outputs disabled)

V

= Input port,

C

Load

= 0, f = 1 MHz,

pF

CC

L

V = Output Port EN = GND (outputs disabled)

C

V = Input port,

CC

C

Load

= 0, f = 1 MHz,

PD_VCC

L

V

= Output Port EN = GND (outputs disabled)

V

= Input port,

C

Load

= 0, f = 1 MHz,

CC

L

V = Output Port EN = GND (outputs disabled)

18.V

is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

CC

19.V is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

L

20.Typical values are at T = +25°C

A

www.onsemi.com

9

NLSX5014

V

L

V

CC

V

L

V

CC

EN

I/O V

L

I/O V

L

I/O V

CC

Source

C

IOVL

C

IOVCC

Source

t

v

I/O V

t

RISE/FALL

v 3 ns

RISE/FALL

I/O V

CC

L

3 ns

90%

50%

10%

90%

50%

10%

t

PD_VCC−VL

PD_VL−VCC

I/O V

CC

L

90%

50%

10%

90%

50%

10%

t

R−VCC

t

R−VL

F−VCC

F−VL

Figure 3. Driving I/O V_LTest Circuit and Timing

Figure 4. Driving I/O V_CCTest Circuit and Timing

V

CC

2xV

CC

OPEN

R

1

PULSE

GENERATOR

DUT

R

T

C

L

R

L

Test

Switch

t

, t

Open

PZH PHZ

, t

2 x V

CC

PZL PLZ

C = 15 pF or equivalent (Includes jig and probe capacitance)

L

R = R = 50 kW or equivalent

L

T

1

OUT

R = Z

of pulse generator (typically 50 W)

Figure 5. Test Circuit for Enable/Disable Time Measurement

t

F

V

R

L

50%

EN

V

CC

90%

50%

Input

GND

10%

GND

t

PLZ

PZL

t

PHL

PLH

HIGH

IMPEDANCE

90%

50%

10%

50%

Output

10%

90%

V

OL

t

PHZ

PZH

t

R

t

F

V

OH

50%

Output

HIGH

IMPEDANCE

Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement

www.onsemi.com

10

NLSX5014

IMPORTANT APPLICATIONS INFORMATION

Level Translator Architecture

V pins to a high impedance state. Normal translation

L

The NLSX5014 auto−sense translator provides

bi−directional logic voltage level shifting to transfer data

in multiple supply voltage systems. These level translators

operation occurs when the EN pin is equal to a logic high

signal. The EN pin is referenced to the V supply and has

L

Over−Voltage Tolerant (OVT) protection.

have two supply voltages, V and V , which set the logic

L

CC

Uni−Directional versus Bi−Directional Translation

levels on the input and output sides of the translator. When

used to transfer data from the I/O V to the I/O V ports,

The NLSX5014 translator can function as

a

L

CC

non−inverting uni−directional translator. One advantage of

using the translator as a uni−directional device is that each

I/O pin can be configured as either an input or output. The

configurable input or output feature is especially useful in

applications such as SPI that use multiple uni−directional

I/O lines to send data to and from a device. The flexible I/O

port of the auto sense translator simplifies the trace

connections on the PCB.

input signals referenced to the V supply are translated to

L

output signals with a logic level matched to V . In a

CC

similar manner, the I/O V to I/O V translation shifts

CC

L

input signals with a logic level compatible to V to an

CC

output signal matched to V .

L

The NLSX5014 translator consists of bi−directional

channels that independently determine the direction of the

data flow without requiring a directional pin. One−shot

circuits are used to detect the rising or falling input signals.

In addition, the one−shots decrease the rise and fall times

of the output signal for high−to−low and low−to−high

transitions.

Power Supply Guidelines

The values of the V and V supplies can be set to

L

CC

anywhere between 0.9 and 4.5 V. Design flexibility is

maximized because V may be either greater than or less

L

than the V supply. In contrast, the majority of the

competitive auto sense translators has a restriction that the

CC

Input Driver Requirements

Auto−sense translators such as the NLSX5014 have a

wide bandwidth, but a relatively small DC output current

rating. The high bandwidth of the bi−directional I/O circuit

is used to quickly transform from an input to an output

driver and vice versa. The I/O ports have a modest DC

current output specification so that the output driver can be

over driven when data is sent in the opposite direction. For

proper operation, the input driver to the auto−sense

translator should be capable of driving 2 mA of peak output

current. The bi−directional configuration of the translator

results in both input stages being active for a very short time

period. Although the peak current from the input signal

circuit is relatively large, the average current is small and

consistent with a standard CMOS input stage.

value of the V supply must be equal to less than (V

−

L

CC

0.4) V.

The sequencing of the power supplies will not damage

the device during power−up operation. In addition, the I/O

V

CC

and I/O V pins are in the high impedance state if

L

either supply voltage is equal to 0 V. For optimal

performance, 0.01 to 0.1 mF decoupling capacitors should

be used on the V and V power supply pins. Ceramic

L

CC

capacitors are a good design choice to filter and bypass any

noise signals on the voltage lines to the ground plane of the

PCB. The noise immunity will be maximized by placing

the capacitors as close as possible to the supply and ground

pins, along with minimizing the PCB connection traces.

The NLSX5014 translators have a power down feature

that provides design flexibility. The output ports are

Enable Input (EN)

The NLSX5014 translator has an Enable pin (EN) that

provides tri−state operation at the I/O pins. Driving the

Enable pin to a low logic level minimizes the power

disabled when either power supply is off (V or V = 0 V).

This feature causes all of the I/O pins to be in the power

saving high impedance state.

L

CC

consumption of the device and drives the I/O V and I/O

CC

www.onsemi.com

11

NLSX5014

PACKAGE DIMENSIONS

UQFN12 1.7x2.0, 0.4P

CASE 523AE

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

D

A B

2. CONTROLLING DIMENSION: MILLIMETERS

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM TERMINAL TIP.

L1

PIN 1 REFERENCE

4. MOLD FLASH ALLOWED ON TERMINALS

ALONG EDGE OF PACKAGE. FLASH 0.03

MAX ON BOTTOM SURFACE OF

TERMINALS.

5. DETAIL A SHOWS OPTIONAL

CONSTRUCTION FOR TERMINALS.

DETAIL A

E

NOTE 5

0.10

C

2X

MILLIMETERS

TOP VIEW

DIM MIN

MAX

0.55

0.05

A

A1

A3

b

0.45

0.00

0.127 REF

DETAIL B

A

0.15

0.25

0.05

C

DETAIL B

OPTIONAL

CONSTRUCTION

D

1.70 BSC

2.00 BSC

0.40 BSC

E

e

12X

C

K

0.20

----

0.55

0.03

A1

SEATING

PLANE

C

L

0.45

0.00

0.15 REF

A3

SIDE VIEW

L1

L2

8X

K

5

1

7

DETAIL A

12X L

e

MOUNTING FOOTPRINT

SOLDERMASK DEFINED

2.00

11

12X

b

0.10

1

L2

M

C A B

C

BOTTOM VIEW

0.05

NOTE 3

0.40

0.32

PITCH

2.30

11X

0.22

12X

0.69

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

www.onsemi.com

12

NLSX5014

PACKAGE DIMENSIONS

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE L

NOTES:

D

A

B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

14

8

7

A3

E

H

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

L

DETAIL A

1

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

13X b

M

B

0.25

A

A1

A3

b

D

E

1.35

0.10

0.19

0.35

8.55

3.80

1.75 0.054 0.068

0.25 0.004 0.010

0.25 0.008 0.010

0.49 0.014 0.019

8.75 0.337 0.344

4.00 0.150 0.157

M

S

B

0.25

C A

DETAIL A

h

A

X 45

_

e

H

h

L

1.27 BSC

0.050 BSC

6.20 0.228 0.244

0.50 0.010 0.019

1.25 0.016 0.049

5.80

0.25

0.40

0

0.10

M

A1

e

M

7

0

7

_

SEATING

PLANE

C

SOLDERING FOOTPRINT*

6.50

14X

1.18

1

1.27

PITCH

14X

0.58

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

www.onsemi.com

13

NLSX5014

PACKAGE DIMENSIONS

TSSOP−14

DT SUFFIX

CASE 948G

ISSUE C

NOTES:

14X K REF

1. DIMENSIONING AND TOLERANCING PER

M

S

V

ANSI Y14.5M, 1982.

0.10 (0.004)

T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

S

0.15 (0.006) T U

N

0.25 (0.010)

14

8

2X L/2

M

B

L

N

−U−

PIN 1

IDENT.

F

7

1

DETAIL E

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

S

K

0.15 (0.006) T U

A

−V−

K1

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

A

B

C

D

F

G

H

J

4.90

4.30

−−−

0.05

0.50

0.65 BSC

0.50

0.09

5.10 0.193 0.200

4.50 0.169 0.177

J J1

1.20

−−− 0.047

0.15 0.002 0.006

0.75 0.020 0.030

SECTION N−N

0.026 BSC

0.60 0.020 0.024

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

−W−

C

J1 0.09

0.19

K

0.10 (0.004)

K1 0.19

L

M

6.40 BSC

0.252 BSC

SEATING

PLANE

−T−

H

G

DETAIL E

D

0

8

0

8

_

SOLDERING FOOTPRINT

7.06

1

0.65

PITCH

0¹.3^4X6

14X

1.26

DIMENSIONS: MILLIMETERS

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14


型号：	NLSX5014_18
厂家：	ONSEMI
描述：	4-Bit 100 Mb/s Configurable Dual-Supply Level Translator
文件：	总14页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NLSX5014_18 [ONSEMI]

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