NLU1GT86CMX1TCG [ONSEMI]
Single 2-Input Exclusive OR Gate, TTL Level LSTTL-Compatible Inputs; 单路2输入异或门， TTL电平输入通道兼容输入
| 型号： | NLU1GT86CMX1TCG |
| 厂家： | 
ONSEMI |
| 描述： | Single 2-Input Exclusive OR Gate, TTL Level LSTTL-Compatible Inputs |
| 文件： | 总8页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLU1GT86
Single 2-Input Exclusive OR
Gate, TTL Level
LSTTL-Compatible Inputs
The NLU1GT86 MiniGatet is an advanced CMOS high-speed
2-input Exclusive OR gate in ultra-small footprint.
The device input is compatible with TTL-type input thresholds and
the output has a full 5.0 V CMOS level output swing.
The NLU1GT86 input and output structures provide protection
when voltages up to 7.0 V are applied, regardless of the supply
voltage.
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MARKING
DIAGRAMS
UDFN6
MU SUFFIX
CASE 517AA
6M
1
Features
•ꢀHigh Speed: t = 3.1 ns (Typ) @ V = 5.0 V
PD
CC
ULLGA6
1.0 x 1.0
CASE 613AD
6M
6M
6M
•ꢀLow Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
1
•ꢀTTL-Compatible Input: V = 0.8 V; V = 2.0 V
IL
IH
•ꢀCMOS-Compatible Output:
V
OH
> 0.8 V ; V < 0.1 V @ Load
CC OL CC
ULLGA6
1.2 x 1.0
CASE 613AE
•ꢀPower Down Protection Provided on inputs
•ꢀBalanced Propagation Delays
•ꢀUltra-Small Packages
1
•ꢀThese are Pb-Free Devices
ULLGA6
1.45 x 1.0
CASE 613AF
1
IN B
IN A
GND
1
2
3
6
5
V
CC
6
= Device Marking
= Date Code
M
NC
PIN ASSIGNMENT
1
IN B
IN A
2
3
4
5
6
4
OUT Y
GND
OUT Y
NC
Figure 1. Pinout (Top View)
V
CC
FUNCTION TABLE
IN A
IN B
= 1
OUT Y
Input
Output
A
B
Y
Figure 2. Logic Symbol
L
L
L
H
L
L
H
H
L
H
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©ꢀ Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 2
1
Publication Order Number:
NLU1GT86/D
NLU1GT86
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
-0.5 to +7.0
V
IN
DC Input Voltage
-0.5 to +7.0
V
V
OUT
DC Output Voltage
-0.5 to +7.0
V
I
DC Input Diode Current
V
< GND
< GND
OUT
-20
mA
mA
mA
mA
mA
°C
IK
IN
I
DC Output Diode Current
V
20
OK
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
12.5
O
I
25
CC
I
25
-65 to +150
260
GND
T
STG
T
°C
L
T
150
°C
J
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 150
N/A
V
I
Latchup Performance Above V and Below GND at 125°C (Note 5)
CC
500
mA
LATCHUP
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm-by-1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22-A114-A.
3. Tested to EIA / JESD22-A115-A.
4. Tested to JESD22-C101-A.
5. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
5.5
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
V
IN
5.5
V
V
OUT
Output Voltage
0
5.5
V
T
Operating Free-Air Temperature
Input Transition Rise or Fall Rate
-55
+125
°C
ns/V
A
Dt/DV
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
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2
NLU1GT86
DC ELECTRICAL CHARACTERISTICS
T
= -555C
A
to +1255C
T
A
= 25 5C
Typ
T
= +855C
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Conditions
V
CC
(V)
Unit
V
IH
Low-Level Input
Voltage
3.0
1.4
2.0
1.4
2.0
1.4
2.0
V
4.5 to 5.5
V
Low-Level Input
Voltage
3.0
0.53
0.8
0.53
0.8
0.53
0.8
V
V
IL
4.5 to 5.5
V
OH
High-Level Output
Voltage
V
= V or V
IH
= -50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
IN
IL
I
OH
V
I
I
= V or V
IH
= -4 mA
= -8 mA
IN
OH
OH
IL
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Low-Level Output
Voltage
V
= V or V
IH
= 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IL
I
OL
V
I
I
= V or V
IH
= 4 mA
= 8 mA
IN
OL
OL
IL
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Input Leakage
Current
0 v V v 5.5 V
IN
0 to 5.5
0.1
1.0
1.0
mA
mA
mA
mA
IN
I
Quiescent Supply
Current
0 v V v V
5.5
1.0
20
40
CC
IN
CC
I
Quiescent Supply
Current
V = 3.4 V
IN
5.5
1.35
0.5
1.50
5.0
1.65
10
CCT
I
Output Leakage
Current
V
OUT
= 5.5 V
0.0
OPD
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
f
r
T
= -555C
A
to +1255C
T
A
= 25 5C
Typ
5.0
T
= +855C
A
V
Test
Condition
CC
(V)
Min
Max
11.0
14.5
6.8
Min
Max
13.0
16.5
6.0
Min
Max
Symbol
Parameter
Unit
t
t
,
Propagation Delay, Input A to
Output Y
3.0 to
3.6
C = 15 pF
L
15.5
19.5
10.0
12.0
10.0
ns
PLH
PHL
C = 50 pF
L
6.2
4.5 to
5.5
C = 15 pF
L
3.1
C = 50 pF
L
4.2
8.8
10.0
10
C
Input Capacitance
5.5
10
pF
pF
IN
C
Power Dissipation
Capacitance (Note 6)
5.0
11
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without
= C • V • f + I . C is used to determine the no-load
PD CC in CC PD
PD
load. Average operating current can be obtained by the equation I
CC(OPR)
2
dynamic power consumption: P = C • V
• f + I • V
in CC CC.
D
PD
CC
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3
NLU1GT86
Input A or B
V
CC
50%
50%
GND
t
t
PLH
PHL
V
OH
Output Y
50% V
CC
V
OL
Figure 3. Switching Waveforms
V
CC
OUTPUT
INPUT
C
L*
*Includes all probe and jig capacitance.
A 1-MHz square input wave is recommended for propagation delay tests.
Figure 4. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
NLU1GT86MUTCG
UDFN6
(Pb-Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NLU1GT86AMX1TCG
NLU1GT86BMX1TCG
NLU1GT86CMX1TCG
ULLGA6, 1.45 x 1.0, 0.5P
(Pb-Free)
ULLGA6, 1.2 x 1.0, 0.4P
(Pb-Free)
ULLGA6, 1.0 x 1.0, 0.35P
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NLU1GT86
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA-01
ISSUE C
EDGE OF PACKAGE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
A
B
D
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
E
DETAIL A
Bottom View
(Optional)
MILLIMETERS
2X
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
A
0.10
C
MOLD CMPD
EXPOSED Cu
TOP VIEW
A3
b
0.127 REF
0.25
2X
0.15
0.10
C
C
D
E
e
1.20 BSC
1.00 BSC
0.40 BSC
A3
L
0.30
0.40
0.15
0.50
(A3)
L1 0.00
L2 0.40
0.10
0.08
A1
DETAIL B
Side View
(Optional)
A
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
5X
SEATING
PLANE
10X
C
SIDE VIEW
6X
C
0.48
0.22
A1
5X L
3
1
L2
1.18
6X b
1
0.35
PITCH
6
4
0.53
0.10
0.05
C
A B
PKG
OUTLINE
e
C
NOTE 3
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
NLU1GT86
PACKAGE DIMENSIONS
ULLGA6 1.0x1.0, 0.35P
CASE 613AD-01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
REFERENCE
E
MILLIMETERS
DIM MIN
---
A1 0.00
MAX
0.40
0.05
0.22
0.10
C
A
TOP VIEW
b
D
E
e
0.12
0.10
C
1.00 BSC
1.00 BSC
0.35 BSC
0.05
0.05
C
C
L 0.25
L1 0.30
0.35
0.40
A
SEATING
PLANE
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
5X
6X
SIDE VIEW
A1
C
6X
0.48
0.22
e
NOTE 4
5X L
3
1
1.18
L1
1
0.35
0.53
PKG
OUTLINE
PITCH
6
4
6X b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A B
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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6
NLU1GT86
PACKAGE DIMENSIONS
ULLGA6 1.2x1.0, 0.4P
CASE 613AE-01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
PIN ONE
REFERENCE
E
MILLIMETERS
DIM MIN
---
A1 0.00
MAX
0.40
0.05
0.25
0.10
C
A
TOP VIEW
b
D
E
e
0.15
0.10
C
1.20 BSC
1.00 BSC
0.40 BSC
0.05
0.05
C
C
L 0.25
L1 0.35
0.35
0.45
A
SEATING
PLANE
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
5X
6X
SIDE VIEW
A1
C
6X
0.49
0.26
e
NOTE 4
5X L
3
1
1.24
L1
1
0.53
0.40
PITCH
PKG
OUTLINE
6
4
6X b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A B
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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7
NLU1GT86
PACKAGE DIMENSIONS
ULLGA6 1.45x1.0, 0.5P
CASE 613AF-01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
A
B
D
PIN ONE
REFERENCE
E
MILLIMETERS
DIM MIN
---
A1 0.00
MAX
0.40
0.05
0.25
A
0.10
C
TOP VIEW
b
D
E
e
0.15
0.10
C
1.45 BSC
1.00 BSC
0.50 BSC
L
0.25
L1 0.30
0.35
0.40
0.05
0.05
C
C
A
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
5X
SEATING
PLANE
6X
SIDE VIEW
6X
A1
C
0.49
0.30
e
NOTE 4
5X L
3
1
1.24
L1
1
0.53
PKG
OUTLINE
0.50
PITCH
6
4
6X b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A B
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NLU1GT86/D
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