NLV14011UBDG [ONSEMI]
UB-Suffix Series CMOS Gates;
| 型号： | NLV14011UBDG |
| 厂家： | 
ONSEMI |
| 描述： | UB-Suffix Series CMOS Gates 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting non−buffered functions.
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Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications
SOIC−14
D SUFFIX
CASE 751A
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
MARKING DIAGRAM
• Pin−for−Pin Replacements for Corresponding CD4000 Series UB
14
Suffix Devices
140xxUG
AWLYWW
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
• This Device is Pb−Free and is RoHS Compliant
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
WW, W = Work Week
= Pb−Free Package
V
DD
DC Supply Voltage Range
G
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation, per Package
(Note 1)
500
mW
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
T
Lead Temperature
L
(8−Second Soldering)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V ≤ (V or V ) ≤ V .
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
July, 2014 − Rev. 10
MC14001UB/D
MC14001UB, MC14011UB
LOGIC DIAGRAMS
MC14001UB
Quad 2−Input
NOR Gate
MC14011UB
Quad 2−Input
NAND Gate
1
1
2
3
3
2
5
5
4
4
6
6
8
8
10
11
10
11
9
9
12
12
13
13
V
= PIN 14
= PIN 7
FOR ALL DEVICES
DD
V
SS
PIN ASSIGNMENTS
MC14001UB
MC14011UB
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
IN 1
IN 2
1
2
3
4
5
6
14
V
IN 1
IN 2
1
2
3
4
5
6
14
V
DD
A
DD
A
13 IN 2
12 IN 1
13 IN 2
12 IN 1
A
D
A
D
D
OUT
OUT
A
A
D
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
11 OUT
10 OUT
B
D
C
B
D
C
B
B
B
B
9
8
IN 2
IN 1
9
8
IN 2
IN 1
C
C
V
SS
7
V
SS
7
C
C
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2
MC14001UB, MC14011UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
Typ
V
DD
(Note 2)
Vdc
Min
Max
Min
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
in
= 0 or V
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
DD
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
(V = 0.5 Vdc)
“1” Level
Source
Sink
V
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
Vdc
O
IH
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
5.0
5.0
10
–1.0
–0.25
–0.62
–1.8
−
−
−
−
–0.75
–0.2
–0.4
–1.5
–1.7
–0.36
–0.9
−
−
−
−
–0.55
–0.14
–0.15
–1.0
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
–3.5
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.1
3.4
0.88
2.25
8.8
−
−
−
0.36
0.7
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
I
T
5.0
10
15
I = (0.3 mA/kHz) f + I /N
T DD
I = (0.6 mA/kHz) f + I /N
T
DD
Per Gate C = 50 pF)
I = (0.8 mA/kHz) f + I /N
T
L
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mH (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
L
DD
SS
per package.
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Vdc
(Note 6)
Output Rise Time
t
ns
TLH
THL
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
−
−
−
180
90
65
360
180
130
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time
t
, t
PLH PHL
t
t
t
, t
= (1.7 ns/pF) C + 30 ns
= (0.66 ns/pF) C + 22 ns
L
= (0.50 ns/pF) C + 15 ns
L
5.0
10
15
−
−
−
90
50
40
180
100
80
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
MC14001UB, MC14011UB
ORDERING INFORMATION
Device
†
Package
Shipping
MC14001UBDG
SOIC−14
(Pb−Free)
55 Units / Rail
55 Units / Rail
NLV14001UBDG*
MC14001UBDR2G
NLV14001UBDR2G*
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14
(Pb−Free)
MC14011UBDG
SOIC−14
(Pb−Free)
55 Units / Rail
55 Units / Rail
NLV14011UBDG*
MC14011UBDR2G
NLV14011UBDR2G*
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
20 ns
20 ns
V
DD
V
INPUT
DD
14
90%
50%
10%
INPUT
*
OUTPUT
PULSE
GENERATOR
0 V
V
t
t
PLH
PHL
C
OH
L
90%
50%
10%
OUTPUT
INVERTING
V
OL
7
V
SS
*All unused inputs of AND, NAND gates must be
t
t
TLH
THL
connected to V
.
DD
All unused inputs of OR, NOR gates must be
connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
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4
MC14001UB, MC14011UB
MC14001UB CIRCUIT SCHEMATIC
MC14011UB CIRCUIT SCHEMATIC
(1/4 of Device Shown)
V
DD
3
14 10
14 V
DD
1
2
8
9
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
6
5
13
12
7 V
SS
4
7
11
V
SS
16
14
12
10
8.0
6.0
4.0
2.0
0
16
14
V
= 15 Vdc
V
= 15 Vdc
DD
T = +ꢀ25°C
DD
Unused input
connected to
A
Unused input
b
a
connected to
.
V
SS
.
12
V
SS
a
One input only
Both inputs
10 Vdc
10 Vdc
a T = +ꢀ125°C
A
10
b
b T = -ꢀ55°C
A
8.0
6.0
4.0
8.0
6.0
b
a
a
b
5.0 Vdc
5.0 Vdc
15 Vdc
10 Vdc
a
b
4.0
2.0
0
a
b
a
b
2.0
0
0
2.0 4.0 6.0 8.0 10 12 14 16
0
2.0 4.0 6.0 8.0 10 12 14 16
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 2. Typical Voltage and
Current Transfer Characteristics
Figure 3. Typical Voltage Transfer
Characteristics versus Temperature
10
8.0
6.0
4.0
2.0
0
0
-ꢀ2.0
-ꢀ4.0
-ꢀ6.0
-ꢀ8.0
-ꢀ10
c
a
15 Vdc
b
a
c
V
= -ꢀ5.0 Vdc
GS
b
V
= 10 Vdc
GS
a
b
a T = -ꢀ55°C
b T = +ꢀ25°C
T = +ꢀ125°C
A
c
A
c
A
a T = -ꢀ55°C
b T = +ꢀ25°C
c
A
c
A
T = +ꢀ125°C
A
b
-ꢀ10 Vdc
a
c
c
-ꢀ15 Vdc
b
b
5.0 Vdc
a
a
-ꢀ10
-ꢀ8.0
-ꢀ6.0
-ꢀ4.0
-ꢀ2.0
0
0
2.0
4.0
, DRAIN VOLTAGE (Vdc)
DS
6.0
8.0
10
V
DS
, DRAIN VOLTAGE (Vdc)
V
Figure 4. Typical Output Source Characteristics
Figure 5. Typical Output Sink Characteristics
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5
MC14001UB, MC14011UB
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC14001UB/D
相关型号：
NLV14013BDTR2G
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, HALOGEN FREE AND ROHS COMPLIANT, TSSOP-14
ROCHESTER
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