NLV14049UBDTR2G [ONSEMI]
六路逆变器;
| 型号： | NLV14049UBDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 六路逆变器 |
| 文件： | 总8页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
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MARKING
supply voltage, V . The input−signal high level (V ) can exceed the
DD
IH
V
DD
supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V = 5.0 V, V v 0.4 V, I ≥ 3.2 mA). Note that pins
DIAGRAMS
DD
OL
OL
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
16
1
PDIP−16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWWG
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V can exceed V
16
SOIC−16
D SUFFIX
CASE 751B
14049UBG
AWLYWW
IN
DD
1
• Improved ESD Protection on All Inputs
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
16
14
049UB
ALYW G
G
TSSOP−16
DT SUFFIX
CASE 948F
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
Unit
16
V
DD
DC Supply Voltage Range
−0.5 to +18.0
−0.5 to +18.0
V
V
SOEIAJ−16
F SUFFIX
CASE 966
V
in
Input Voltage Range
(DC or Transient)
MC14049UB
ALYWG
V
out
Output Voltage Range
(DC or Transient)
−0.5 to V
V
DD
1
+0.5
I
Input Current
(DC or Transient) per Pin
10
mA
mA
mW
in
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
I
Output Current
(DC or Transient) per Pin
+45
out
WW, W = Work Week
P
Power Dissipation, per Package (Note 1)
Plastic
SOIC
G or G
= Pb−Free Package
D
825
740
(Note: Microdot may be in either location)
T
Ambient Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
Storage Temperature Range
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
T
Lead Temperature (8−Second Soldering)
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V pin, only. Extra precautions
SS
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges
V
v V v 18 V and V v V v V are recommended.
SS
in
SS
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 8
MC14049UB/D
MC14049UB
V
DD
3
2
V
1
2
3
4
5
6
7
8
16 NC
DD
OUT
15 OUT
A
F
MC14049UB
4
5
7
IN
14 IN
F
A
OUT
13 NC
B
6
IN
12 OUT
B
E
D
11 IN
OUT
IN
10
E
9
C
10 OUT
C
NC = PIN 13, 16
11
14
12
V
9
IN
D
SS
V
SS
V
DD
= PIN 8
= PIN 1
NC = NO CONNECTION
V
15
SS
Figure 3. Circuit Schematic
Figure 2. Logic Diagram
MC14049UB
Figure 1. Pin Assignment
(1/6 of circuit shown)
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
(Note 2)
Output Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
V
IH
Vdc
“1” Level
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
(V = 0.5 Vdc)
O
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
10
15
– 1.6
– 1.6
– 4.7
−
−
−
– 1.25
– 1.3
– 3.75
– 2.5
– 2.6
– 10
−
−
−
– 1.0
– 1.0
– 3.0
−
−
−
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
I
OL
5.0
10
15
3.75
10
30
−
−
−
3.2
8.0
24
6.0
16
40
−
−
−
2.6
6.6
19
−
−
−
mAdc
(V = 0.4 Vdc)
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
I
in
15
−
0.1
−
0.000
01
0.1
−
1.0
mAdc
Input Capacitance (V = 0)
C
−
−
−
−
10
20
−
−
pF
in
in
Quiescent Current (Per Package)
I
5.0
10
15
−
−
−
1.0
2.0
4.0
−
−
−
0.002
0.004
0.006
1.0
2.0
4.0
−
−
−
30
60
120
mAdc
DD
Total Supply Current (Note 3 and 4)
(Dynamic plus Quiescent, Per Package)
I
T
5.0
10
15
I = (1.8 mA/kHz) f + I
mAdc
T
DD
DD
DD
I = (3.5 mA/kHz) f + I
T
(C = 50 pF on all outputs, all buffers
L
I = (5.3 mA/kHz) f + I
T
switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.002.
T
L
DD
SS
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2
MC14049UB
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Vdc
(Note 6)
Output Rise Time
t
t
ns
TLH
THL
PLH
PHL
t
t
t
= (0.8 ns/pF) C + 60 ns
= (0.3 ns/pF) C + 35 ns
= (0.27 ns/pF) C + 26.5 ns
5.0
10
15
−
−
−
100
50
40
160
100
60
TLH
TLH
TLH
L
L
L
Output Fall Time
ns
ns
ns
t
t
t
= (0.3 ns/pF) C + 25 ns
= (0.12 ns/pF) C + 14 ns
= (0.1 ns/pF) C + 10 ns
5.0
10
15
−
−
−
40
20
15
60
40
30
THL
THL
THL
L
L
L
Propagation Delay Time
t
t
t
t
t
= (0.38 ns/pF) C + 61 ns
= (0.20 ns/pF) C + 30 ns
= (0.11 ns/pF) C + 24.5 ns
5.0
10
15
−
−
−
80
40
30
120
65
50
PLH
PLH
PLH
L
L
L
Propagation Delay Time
t
t
t
= (0.38 ns/pF) C + 11 ns
5.0
10
15
−
−
−
30
15
10
60
30
20
PHL
PHL
PHL
L
= (0.12 ns/PF) C + 9 ns
L
= (0.11 ns/pF) C + 4.5 ns
L
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
ORDERING INFORMATION
†
Device
Package
Shipping
MC14049UBCPG
PDIP−16
500 Units / Tape & Ammunition Box
48 Units / Rail
(Pb−Free)
MC14049UBDG
SOIC−16
(Pb−Free)
NLV14049UBDG*
MC14049UBDR2G
NLV14049UBDR2G*
MC14049UBDTELG
SOIC−16
(Pb−Free)
2500 / Tape & Reel
TSSOP−16
(Pb−Free)
96 Units / Rail
MC14049UBDTR2G
MC14049UBFELG
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
18
V
V
= 15 Vdc
= 10 Vdc
DD
15
10
DD
−55°C
V
DD
= 5 Vdc
5
+125°C
5
10
15
18
V , INPUT VOLTAGE (Vdc)
in
Figure 4. Typical Voltage Transfer Characteristics versus Temperature
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3
MC14049UB
V
1
V
1
DD
DD
I
I
OL
OH
V
OH
V
OL
V
SS
8
V
SS
8
V
DS
= V - V
OH
V = V
DD OL
DD
0
-ꢀ10
-ꢀ20
-ꢀ30
-ꢀ40
-ꢀ50
160
120
80
V
= 15 Vdc
= 10 Vdc
GS
V
GS
= 5.0 Vdc
V
GS
V
GS
= 10 Vdc
MAXIMUM CURRENT LEVEL
40
V
GS
= 15 Vdc
V
GS
= 5.0 Vdc
MAXIMUM CURRENT LEVEL
0
-ꢀ10
-ꢀ8.0
-ꢀ6.0
-ꢀ4.0
-ꢀ2.0
0
0
2.0
4.0
6.0
8.0
10
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V , DRAIN-TO-SOURCE VOLTAGE (Vdc)
DS
Figure 5. Typical Output Source Characteristics
Figure 6. Typical Output Sink Characteristics
V
1
DD
PULSE
V
out
GENERATOR
1200
V
in
1100
1000
C
8
V
SS
L
900
825
800
740
700
600
500
400
300
200
20 ns
20 ns
V
DD
INPUT
90%
50%
(P) PDIP
10%
V
V
SS
t
(D) SOIC
t
PHL
PLH
OH
175 mW (P)
120 mW (D)
90%
50%
10%
OUTPUT
100
0
25
V
OL
50
75
100
125
150
175
t
t
THL
TLH
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Ambient Temperature Power Derating
Figure 8. Switching Time Test Circuit
and Waveforms
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4
MC14049UB
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
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5
MC14049UB
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC14049UB
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
M
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MC14049UB
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
NOTES:
ꢁꢂ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
16
9
ꢁꢂ2. CONTROLLING DIMENSION: MILLIMETER.
ꢁꢂ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
M
_
E
ꢁꢂ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢁꢂ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
---
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
---
0.05
0.35
0.10
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.20 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50
5.45 0.201
0.390
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
1
Z
0.78
---
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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