NLV74HC125ADTR2G [ONSEMI]
Quad 3-State Noninverting Buffers;
| 型号： | NLV74HC125ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 3-State Noninverting Buffers |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
Features
OE1
A1
1
2
14
13 OE4
12
V
CC
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
Y1
3
4
A4
OE2
11 Y4
• Low Input Current: 1.0 mA
A2
Y2
5
6
10 OE3
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
9
8
A3
Y3
GND
7
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MARKING DIAGRAMS
14
14
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
HC
12xA
ALYWG
G
HC12xAG
AWLYWW
Compliant
LOGIC DIAGRAM
1
1
HC125A
HC126A
SOIC−14 NB
TSSOP−14
Active−Low Output Enables
Active−High Output Enables
x
= 5, 6
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
2
3
2
3
A1
A1
Y1
Y2
Y3
Y1
Y2
Y3
1
5
1
5
W, WW = Work Week
OE1
A2
OE1
A2
G or G
= Pb−Free Package
6
6
(Note: Microdot may be in either location)
4
9
4
9
OE2
A3
OE2
A3
FUNCTION TABLE
HC125A
HC126A
8
8
Inputs Output
Inputs Output
A
OE
Y
A
OE
Y
10
12
10
12
OE3
A4
OE3
A4
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
11
11
Y4
Y4
13
13
OE4
OE4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
PIN 14 = V
CC
PIN 7 = GND
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 15
MC74HC125A/D
MC74HC125A, MC74HC126A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to +7.0
CC
V
–0.5 to V + 0.5
V
in
out
CC
V
–0.5 to V + 0.5
V
CC
I
20
35
75
mA
mA
mA
mW
in
I
DC Output Current, per Pin
out
CC
cuit. For proper operation, V and
in
V
out
should be constrained to the
I
DC Supply Current, V and GND Pins
CC
range GND v (V or V ) v V
.
in
out
CC
P
D
Power Dissipation in Still Air
SOIC Package†
TSSOP Package†
500
450
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
Unused outputs must be left open.
T
Storage Temperature
–65 to +150
_C
_C
CC
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
L
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
Max
Unit
V
V
CC
6.0
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
Operating Temperature, All Package Types
–55
+125
_C
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HC125A, MC74HC126A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
–55 to
V
25_C
Symbol
Parameter
Test Conditions
= V – 0.1 V
|I | v 20 mA
v 85_C v 125_C
Unit
V
IH
Minimum High−Level Input Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
out
CC
out
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
|I | v 20 mA
out
V
= V
|I | v 3.6 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
|I | v 20 mA
out
V
= V
|I | v 3.6 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
I
Maximum Input Leakage Current
V
in
= V or GND
6.0
6.0
0.1
0.5
1.0
5.0
1.0
10
mA
mA
in
CC
I
Maximum Three−State Leakage
Current
Output in High−Impedance State
= V or V
OZ
V
in
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply Current
(per Package)
V
= V or GND
= 0 mA
6.0
4.0
40
160
mA
CC
in
CC
I
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
–55 to
V
CC
25_C
v 85_C
v 125_C
V
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
36
18
15
115
45
135
60
ns
PLH
t
PHL
23
20
27
23
,
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
120
45
24
150
60
30
180
80
36
ns
ns
ns
PLZ
t
PHZ
20
26
31
,
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
90
36
18
15
115
45
23
135
60
27
PZL
t
PZH
20
23
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
TLH
t
THL
C
Maximum Input Capacitance
−
−
10
15
10
15
10
15
pF
pF
in
C
Maximum 3−State Output Capacitance (Output in High−Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
30
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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3
MC74HC125A, MC74HC126A
SWITCHING WAVEFORMS
V
CC
OE (HC125A)
OE (HC126A)
50%
50%
t
t
f
r
GND
V
CC
90%
50%
10%
V
CC
INPUT A
GND
GND
t
PHL
t
PLH
t
t
PZL
PLZ
90%
50%
10%
OUTPUT Y
HIGH
IMPEDANCE
50%
OUTPUT Y
OUTPUT Y
10%
90%
V
OL
t
t
THL
TLH
t
t
PZH
PHZ
V
OH
50%
HIGH
Figure 1.
IMPEDANCE
Figure 2.
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t and t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
V
CC
OE
A
Y
HC125A
(1/4 OF THE DEVICE)
V
CC
OE
A
Y
HC126A
(1/4 OF THE DEVICE)
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4
MC74HC125A, MC74HC126A
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC125ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
MC74HC125ADR2G
MC74HC125ADTG
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
MC74HC125ADTR2G
MC74HC126ADG
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
55 Units / Rail
SOIC−14 NB
(Pb−Free)
MC74HC126ADR2G
MC74HC126ADTR2G
NLV74HC125ADG*
NLV74HC125ADR2G*
NLV74HC125ADTG*
NLV74HC125ADTR2G*
NLV74HC126ADR2G*
NLV74HC126ADTR2G*
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
55 Units / Rail
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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5
MC74HC125A, MC74HC126A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
−T−
H
G
0
8
0
8
DETAIL E
_
_
_
_
D
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MC74HC125A, MC74HC126A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74HC125A/D
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