NLV74HC138ADTR2G [ONSEMI]
1-of-8 Decoder/ Demultiplexer;
| 型号： | NLV74HC138ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 1-of-8 Decoder/ Demultiplexer |
| 文件： | 总10页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC138A
1-of-8 Decoder/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC138A decodes a three−bit Address to one−of−eight
active−low outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC138AN
AWLYYWWG
16
16
1
1
16
Features
SOIC−16
D SUFFIX
CASE 751B
HC138AG
AWLYWW
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
1
1
16
• High Noise Immunity Characteristic of CMOS Devices
TSSOP−16
DT SUFFIX
CASE 948F
HC
138A
ALYWG
G
16
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
1
• Chip Complexity: 100 FETs or 29 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
W, WW = Work Week
Compliant
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
July, 2012 − Rev. 12
MC74HC138A/D
MC74HC138A
1
15
14
13
12
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
ADDRESS
2
A1
A2
A0
A1
1
2
3
4
5
6
7
8
16
15
INPUTS
V
CC
3
Y0
ACTIVE-LOW
OUTPUTS
11
10
14 Y1
13 Y2
12 Y3
A2
CS2
9
7
CS3
CS1
11
10
9
Y4
6
4
Y7
Y5
Y6
CS1
CS2
CS3
CHIP-
SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
GND
5
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Inputs
Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H = high level (steady state); L = low level (steady state); X = don’t care
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC138ANG
PDIP−16
500 Units / Rail
48 Units / Rail
(Pb−Free)
MC74HC138ADG
SOIC−16
(Pb−Free)
MC74HC138ADR2G
MC74HC138ADTR2G
NLV74HC138ADR2G*
NLV74HC138ADTR2G*
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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2
MC74HC138A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
DC Supply Current, V and GND Pins
range GND v (V or V ) v V
.
CC
CC
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
−
Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 .W/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V , V
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
0
V
V
in out
CC
T
A
– 55
+ 125
_C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
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3
MC74HC138A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
−55_C to 25_C
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
out
CC
Voltage
out
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I | v 20 mA
out
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
OH
Minimum High−Level Output
Voltage
IH
|I | v 20 mA
out
V
= V or V |I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
in
IH
IL out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low−Level Output
V
IH
IL
Voltage
|I | v 20 mA
out
V
= V or V |I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
IH
IL out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage
Current
V
V
= V or GND
6.0
0.1
1.0
1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
6.0
4
40
160
CC
in
CC
I
= 0 mA
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
CC
V
−55_C to 25_C
v 85_C v 125_C
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)
2.0
3.0
4.5
6.0
135
90
170
125
34
205
165
41
ns
PLH
t
PHL
27
23
29
35
,
Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
85
22
140
100
28
165
125
33
ns
ns
ns
PLH
t
PHL
19
24
28
,
Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 3 and 4)
2.0
3.0
4.5
6.0
120
90
24
150
120
30
180
150
36
PLH
t
PHL
20
26
31
,
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
TLH
t
THL
19
C
Maximum Input Capacitance
−
10
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
55
C
Power Dissipation Capacitance (Per Package)*
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74HC138A
SWITCHING WAVEFORMS
t
r
t
f
VALID
VALID
V
CC
90%
50%
10%
V
INPUT CS1
OUTPUT Y
CC
INPUT A
50%
GND
GND
t
t
PLH
PHL
t
t
PHL
PLH
90%
50%
10%
OUTPUT Y
50%
t
t
TLH
THL
Figure 1.
Figure 2.
TEST POINT
OUTPUT
t
f
t
r
V
CC
90%
INPUT
50%
10%
DEVICE
UNDER
TEST
GND
CS2, CS3
t
t
PLH
C *
L
PHL
90%
50%
10%
OUTPUT Y
t
t
TLH
THL
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
OUTPUTS
Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Active−low Decoded outputs. These outputs assume a
low level when addressed and the chip is selected. These
outputs remain high when not addressed or the chip is not
selected.
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
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5
MC74HC138A
EXPANDED LOGIC DIAGRAM
15
Y0
14
13
Y1
Y2
1
2
3
A0
A1
A2
12
11
Y3
Y4
10
Y5
5
4
CS3
CS2
9
7
Y6
Y7
6
CS1
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6
MC74HC138A
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
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7
MC74HC138A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74HC138A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC74HC138A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local
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MC74HC138A/D
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