NLV74HC151ADR2G [ONSEMI]
8-Input Data Selector/Multiplexer;
| 型号： | NLV74HC151ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Input Data Selector/Multiplexer |
| 文件： | 总7页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC151A
8-Input Data
Selector/Multiplexer
High−Performance Silicon−Gate CMOS
The MC74HC151 is identical in pinout to the LS151. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Strobe pin must be at a low
level for the selected data to appear at the outputs. If Strobe is high, the
Y output is forced to a low level and the Y output is forced to a high
level.
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
HC151AG
AWLYWW
16
1
1
The HC151 is similar in function to the HC251 which has 3−state
outputs.
16
TSSOP−16
DT SUFFIX
CASE 948F
HC
151A
ALYWG
G
16
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
1
A
= Assembly Location
= Wafer Lot
= Year
WL, L
YY, Y
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
• These are Pb−Free Devices
D3
D2
1
2
16
V
CC
15 D4
4
D0
3
4
14 D5
13 D6
D1
D0
3
D1
5
6
2
Y
Y
D2
D3
D4
D5
D6
D7
5
6
7
8
12 D7
Y
Y
1
DATA
INPUTS
DATA
OUTPUTS
11
10
9
15
14
13
12
A0
STROBE
GND
A1
A2
FUNCTION TABLE
11
10
9
A0
A1
A2
Inputs
A0
Outputs
ADDRESS
INPUTS
A2
A1
Strobe
Y
Y
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
7
STROBE
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PIN 16 = V
CC
PIN 8 = GND
Figure 1. Logic Diagram
H
D0, D1, …, D7 = the level of the respective D input.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2015 − Rev. 3
MC74HC151A/D
MC74HC151A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
CC
V
−0.5 to V + 0.5
V
in
CC
V
out
−0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
DC Output Current, per Pin
out
CC
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Supply Current, V and GND Pins
in
out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
SOIC Package
TSSOP Package
500
TBD
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
−55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
V
CC
25°C
V
v 85°C
1.5
3.15
4.2
v 125°C
1.5
3.15
4.2
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
Voltage
V
2.0
4.5
6.0
1.5
3.15
4.2
V
out
CC
out
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V − 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
in
= V
|I | v 4.0 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
out
|I | v 5.2 mA
out
V
OL
Maximum Low−Level Output
Voltage
V
= V or V
IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | v 20 mA
out
V
= V or V
|I | v 4.0 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH
IL
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
8
1.0
80
1.0
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
160
CC
in
CC
I
= 0 mA
out
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2
MC74HC151A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
− 55 to
V
CC
25°C
V
v 85°C
v 125°C
Symbol
Parameter
Unit
t
t
t
t
t
t
t
,
Maximum Propagation Delay, Input D to Output Y
(Figures 2 and 7)
2.0
4.5
6.0
170
34
29
215
43
255
51
ns
PLH
t
PHL
37
43
,
Maximum Propagation Delay, Input D to Output Y
(Figures 4 and 7)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Input D to Output Y
(Figures 3 and 7)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
PLH
t
PHL
,
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 7)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
PLH
t
PHL
,
Maximum Propagation Delay, Input D to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
PLH
t
PHL
,
Maximum Propagation Delay, Strobe to Output Y
(Figures 6 and 7)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
PLH
t
PHL
,
Maximum Output Transition Time, Any Output
(Figures 2, 4 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
−
10
10
10
in
Typical @ 25°C, V = 5.0 V
CC
36
C
Power Dissipation Capacitance (Per Package)
pF
PD
PIN DESCRIPTIONS
INPUTS
Strobe (Pin 7)
Strobe. This input pin must be at a low level for the
selected data to appear at the outputs. If the Strobe pin is
high, the Y output is forced to a low level and the Y output
is forced to a high level.
D0, D1, … , D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on any one of these eight binary inputs
may be selected to appear on the output.
CONTROL INPUTS
OUTPUTS
A0, A1, A2 (Pins 11, 10, 9)
Y, Y (Pins 5, 6)
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
Address inputs. The data on these pins are the binary
address of the selected input (see the Function Table).
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3
MC74HC151A
SWITCHING WAVEFORMS
t
r
t
f
VALID
VALID
V
V
CC
CC
90%
50%
10%
50%
INPUT D
INPUT A
t
GND
GND
t
t
t
PHL
PLH
PHL
PLH
90%
50%
10%
OUTPUT
Y OR Y
50%
OUTPUT Y
t
t
THL
TLH
Figure 2.
Figure 3.
t
f
t
r
t
r
t
f
V
CC
V
CC
90%
50%
10%
90%
50%
10%
INPUT D
STROBE
Y
GND
GND
t
t
PHL
PLH
t
t
PLH
PHL
90%
50%
10%
90%
50%
10%
OUTPUT Y
t
t
THL
t
t
TLH
THL
TLH
Figure 4.
Figure 5.
TEST POINT
OUTPUT
t
r
t
f
V
CC
90%
50%
10%
DEVICE
UNDER
TEST
STROBE
Y
GND
t
t
PLH
PHL
C *
L
90%
50%
10%
t
t
TLH
THL
*Includes all probe and jig capacitance
Figure 6.
Figure 7. Test Circuit
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4
MC74HC151A
4
3
2
1
D0
D1
D2
D3
DATA
INPUTS
5
6
15
14
Y
Y
D4
D5
DATA
OUTPUTS
13
12
11
D6
D7
A0
ADDRESS
INPUTS
10
9
A1
A2
7
STROBE
Figure 8. Expanded Logic Diagram
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC151ADG
48 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units / Tube
SOIC−16
(Pb−Free)
MC74HC151ADR2G
NLV74HC151ADR2G*
MC74HC151ADTG
TSSOP−16
(Pb−Free)
MC74HC151ADTR2G
NLV74HC151ADTR2G*
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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5
MC74HC151A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
16X KREF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
M
S
S
0.10 (0.004)
T
U
V
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
N
−V−
A
B
C
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74HC151A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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MC74HC151A/D
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