NLVPCA9306AMUTCG [ONSEMI]

双双向 I2C 总线和 SMBus 电压级转换器;


型号：	NLVPCA9306AMUTCG
厂家：	ONSEMI
描述：	双双向 I2C 总线和 SMBus 电压级转换器接口集成电路转换器
文件：	总13页 (文件大小：409K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

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Dual Bidirectional I²C-bus

and SMBus Voltage-Level

Translator

MARKING

DIAGRAMS

AAF

YWWA

TSSOP−8

DT SUFFIX

CASE 948AL

PCA9306

The PCA9306 is a dual bidirectional I C−bus and SMBus

voltage−level translator with an enable (EN) input.

Features

AK M

ALYW

• 2−bit Bidirectional Translator for SDA and SCL Lines in

US8

US SUFFIX

CASE 493

Mixed−Mode I C−Bus Applications

• Standard−Mode, Fast−Mode, and Fast−Mode Plus I C−Bus and

Commercial

NLV Prefix

SMBus Compatible

• Less Than 1.5 ns Maximum Propagation Delay to Accommodate

Standard−Mode and Fast−Mode I C−Bus Devices and Multiple

UQFN8

AQ MG

Masters

MU SUFFIX

CASE 523AN

• Allows Voltage Level Translation Between:

♦ 1.0 V V

♦ 1.2 V V

♦ 1.8 V V

♦ 2.5 V V

♦ 3.3 V V

and 1.8 V, 2.5 V, 3.3 V or 5 V V

ref(1)

bias(ref)(2)

UDFN8

1.45 x 1.0

CASE 517BZ

P M

and 3.3 V or 5 V V

bias(ref)(2)

and 5 V V

bias(ref)(2)

AAF, AK, AQ, P

= Specific Device Code

= Assembly Location

= Lot Code

• Provides Bidirectional Voltage Translation With No Direction Pin

• Low 3.5 W ON−State Connection Between Input and Output Ports

= Year Code

= Week Code

= Date Code

Provides Less Signal Distortion

W, WW

• Open−Drain I C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)

• 5 V Tolerant I C−Bus I/O Ports to Support Mixed−Mode Signal

= Pb−Free Package

Operation

• High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for

EN = LOW

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

• Lock−Up Free Operation

• Flow Through Pinout for Ease of Printed−Circuit Board Trace

Routing

• Packages Offered:

♦ TSSOP−8, US8, UQFN8, UDFN8

• ESD Performance: 4000 V Human Body Model,

400 V Machine Model

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These are Pb−Free Devices

Publication Order Number:

March, 2022 − Rev. 8

PCA9306/D

PCA9306

Function Description

The PCA9306 is a dual bidirectional I C−bus and SMBus

voltage−level translator with an enable (EN) input, and is

bus. The PCA9306 has a standard open−collector

configuration of the I C−bus. The size of these pull−up

resistors depends on the system, but each side of the

translator must have a pull−up resistor. The device is

designed to work with Standard−mode, Fast−mode and Fast

operational from 1.0 V to 3.6 V (V

) and 1.8 V to 5.5 V

ref(1)

bias(ref)(2)

The PCA9306 allows bidirectional voltage translations

between 1.0 V and 5 V without the use of a direction pin. The

low ON−state resistance (R ) of the switch allows

mode Plus I C−bus devices in addition to SMBus devices.

The maximum frequency is dependent on the RC time

constant, but generally supports > 2 MHz.

connections to be made with minimal propagation delay.

When EN is HIGH, the translator switch is on, and the SCL1

and SDA1 I/O are connected to the SCL2 and SDA2 I/O,

respectively, allowing bidirectional data flow between

ports. When EN is LOW, the translator switch is off, and a

high−impedance state exists between ports.

When the SDA1 or SDA2 port is LOW, the clamp is in the

ON−state and a low resistance connection exists between the

SDA1 and SDA2 ports. Assuming the higher voltage is on

the SDA2 port, when the SDA2 port is HIGH, the voltage on

the SDA1 port is limited to the voltage set by VREF1. When

the SDA1 port is HIGH, the SDA2 port is pulled to the drain

The PCA9306 is not a bus buffer that provides both level

translation and physical capacitance isolation to either side

of the bus when both sides are connected. The PCA9306

only isolates both sides when the device is disabled and

provides voltage level translation when active.

pull−up supply voltage (V

) by the pull−up resistors.

pu(D)

This functionality allows a seamless translation between

higher and lower voltages selected by the user without the

need for directional control. The SCL1/SCL2 channel also

functions as the SDA1/SDA2 channel.

The PCA9306 can be used to run two buses, one at

400 kHz operating frequency and the other at 100 kHz

operating frequency. If the two buses are operating at

different frequencies, the 100 kHz bus must be isolated

when the 400 kHz operation of the other bus is required. If

the master is running at 400 kHz, the maximum system

operating frequency may be less than 400 kHz because of

the delays added by the translator.

All channels have the same electrical characteristics and

there is minimal deviation from one output to another in

voltage or propagation delay. This is a benefit over discrete

transistor voltage translation solutions, since the fabrication

of the switch is symmetrical. The translator provides

excellent ESD protection to lower voltage devices, and at the

same time protects less ESD−resistant devices.

As with the standard I C−bus system, pull−up resistors are

required to provide the logic HIGH levels on the translator’s

FUNCTIONAL DIAGRAM

Figure 1. Logic Diagram

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PCA9306

PIN ASSIGNMENTS

Figure 2. TSSOP−8 / US8 Pinouts

Figure 3. UQFN8 Pinout (Top Thru View)

Figure 4. UDFN8 Pinout (Top Thru View)

Table 1. PIN DESCRIPTION

GND

Description

Ground

VREF1

SCL1

SDA1

SDA2

SCL2

VREF2

Low−voltage side reference supply voltage for SCL1 and SDA1

Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor

Serial data, low−voltage side; connect to VREF1 through a pull−up resistor

Serial data, high−voltage side; connect to VREF2 through a pull−up resistor

Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor

High−voltage side reference supply voltage for SCL2 and SDA2

Switch enable input; connect to VREF2 and pull−up through a high resistor

Table 2. FUNCTION TABLE

Input EN (Note 1)

Function

Low

Disconnect

High

SCL1 = SCL2; SDA1 = SDA2

1. EN is controlled by the V

logic levels and should be at least 1 V higher than V

for best translator operation.

bias(ref)(2)

ref(1)

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PCA9306

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Value

−0.5 to +7.0

128

Unit

Reference Voltage (Note 2)

Reference Bias Voltage (Note 3)

Input Voltage

ref(1)

bias(ref)(2)

I/O

Input / Output Pin Voltage

DC Channel Current

°C

DC Input Diode Current V < GND

−50

STG

Storage Temperature Range

−65 to +150

Lead Temperature, 1 mm from Case for 10 Seconds

Junction Temperature Under Bias

Thermal Resistance (Note 2)

T = 260

°C

T = 150

°C

= 150

= 833

°C/W

Power Dissipation in Still Air at 85°C

Moisture Sensitivity

MSL

Level 1

Flammability Rating Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

ESD

ESD Withstand Voltage Human Body Mode (Note 3)

Machine Model (Note 4)

Charged Device Model (Note 5)

> 4000

> 400

N/A

Latchup Performance Above V and Below GND at 125 °C (Note 6)

100

LATCHUP

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.

3. Tested to EIA / JESD22−A114−A.

4. Tested to EIA / JESD22−A115−A.

5. Tested to JESD22−C101−A.

6. Tested to EIA / JESD78.

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

5.5

Unit

Reference Voltage (1) (Note 7)

VREF1

VREF2

ref(1)

bias(ref)(2)

Reference Bias Voltage (2) (Note 7)

5.5

Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2

Control Pin Input Voltage EN

5.5

I/O

I(EN)

5.5

Pass Switch Current

°C

sw(pass)

Operating Free−Air Temperature

−55

+125

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

7. V

≤ V

−1 V for best results in level shifting applications.

(ref)(1)

bias(ref)(2)

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PCA9306

Table 5. DC ELECTRICAL CHARACTERISTICS

= −555C to +1255C

Typ

(Note 8)

Min

Max

−1.2

Symbol

Parameter

Input Clamping Voltage

Conditions

I = −18 mA; V = 0 V

Unit

I(EN)

High−Level Input Current

V = 5 V; V

= 0 V

I(EN)

EN Pin Input Capacitance

V = 3 V or 0 V

7.1

i(EN)

OFF−State I/O Pin Capacitance

SCLn, SDAn

= 3 V or 0 V; V = 0 V

I(EN)

i/O(off)

ON−State I/O Pin Capacitance

SCLn, SDAn

= 3 V or 0 V;

I(EN)

i/O(on)

= 3 V

9.3

12.5

(2)(3)

ON−State Resistance

SCLn, SDAn

V = 0 V; I = 64 mA

I(EN)

= 4.5 V

2.4

3.0

3.8

9.0

5.0

6.0

8.0

= 3 V

= 2.3 V

= 1.5 V

V = 2.4 V; I = 15 mA

I(EN)

= 4.5 V

4.8

7.5

= 3 V

V = 1.7 V; I = 15 mA

I(EN)

= 2.3 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. All typical values are at T = 25°C.

9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.

ON−state resistance is determined by the lowest voltage of the two terminals.

10.Guaranteed by design.

Table 6. AC ELECTRICAL CHARACTERISTICS (Translating Down) − Values Guaranteed by Design

= −555C to +1255C

Load

Condition

Min

Max

Symbol

Parameter

Test Condition

Unit

SEE FIGURE 4 LOAD SWITCH AT S2 POSITION

Low−to−High Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

= 3.3 V; V = 3.3 V;

C = 15 pF

0.6

1.2

2.0

0.75

1.5

2.0

0.6

1.2

2.0

0.75

1.5

2.5

PLH

PHL

PLH

PHL

I(EN)

= 0 V; V = 1.15 V

C = 30 pF

C = 50 pF

High−to−Low Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

C = 15 pF

C = 30 pF

C = 50 pF

Low−to−High Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

= 2.5 V; V = 2.5 V;

C = 15 pF

I(EN)

= 0 V; V = 0.75 V

C = 30 pF

C = 50 pF

High−to−Low Propagation De-

lay, from (input) SCL2 or

SDA2 to (output) SCL1 or

SDA1

C = 15 pF

C = 30 pF

C = 50 pF

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PCA9306

Table 7. AC ELECTRICAL CHARACTERISTICS (Translating Up) − Values Guaranteed by Design

−555C to +1255C

Min

Max

Symbol

Parameter

Test Condition

Load Condition

Unit

SEE FIGURE 4 LOAD SWITCH AT S1 POSITION

Low−to−High Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

= 3.3 V; V = 2.3 V;

= 1.15 V

0.5

1.0

R = 300 W, C = 15 pF

PLH

PHL

PLH

PHL

I(EN)

= 0 V; V = 3.3 V;

R = 300 W, C = 30 pF

R = 300 W, C = 50 pF

1.75

0.8

High−to−Low Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

R = 300 W, C = 15 pF

R = 300 W, C = 30 pF

1.65

2.75

0.5

R = 300 W, C = 50 pF

Low−to−High Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

= 2.5 V; V = 1.5 V;

R = 300 W, C = 15 pF

I(EN)

= 0 V; V = 2.5 V;

R = 300 W, C = 30 pF

1.0

= 0.75 V

R = 300 W, C = 50 pF

1.75

1.0

High−to−Low Propagation De-

lay, from (input) SCL1 or

SDA1 to (output) SCL2 or

SDA2

R = 300 W, C = 15 pF

R = 300 W, C = 30 pF

2.0

R = 300 W, C = 50 pF

3.3

input

from output under test

S2 (open)

output

A. Load Circuit

B. Timing Diagram

S1 = translating up; S2 = translating down.

C includes probe and jig capacitance.

All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z = 50 W; t ≤ 2 ns; t ≤ 2 ns.

The outputs are measured one at a time, with one transition per measurement.

Figure 5. Load Circuit for Outputs

ORDERING INFORMATION

Device

†

Package

Shipping

PCA9306DTR2G

TSSOP−8

(Pb−Free)

4000 / Tape & Reel

3000 / Tape & Reel

PCA9306AMUTCG

NLVPCA9306AMUTCG*

PCA9306FMUTAG

UQFN8

(Pb−Free)

UDFN8

(Pb−Free)

3000 / Tape & Reel

PCA9306FMUTCG

UDFN8

(Pb−Free)

PCA9306USG

NLV9306USG*

US8

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

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PCA9306

APPLICATION INFORMATION

PU(D)

= 3.3 V

(Note 1)

200 kW

= 1.8 V

(Note 1)

REF(1)

PCA9306

VREF1

VREF2

SCL1

SCL2

SDA2

SCL

I C−Bus

MASTER

I C−Bus

DEVICE

SDA1

SDA

GND

1. The applied voltages at V

operation.

and V

should be such that V

is at least 1 V higher than V

for best translator

ref(1)

pu(D)

bias(ref)(2)

ref(1)

Figure 6. Typical Application (Switch Always Enabled)

PU(D)

= 3.3 V

3.3 V Enable Signal (Note 2)

OFF ON

200 kW

= 1.8 V

(Note 2)

REF(1)

PCA9306

VREF1

VREF2

SCL1

SCL2

SDA2

SCL

I C−Bus

MASTER

I C−Bus

DEVICE

SDA1

SDA

GND

2. In the Enabled mode, the applied enable voltage and the applied voltage at V

should be such that V

is at least 1 V

ref(1)

bias(ref)(2)

higher than V

for best translator operation.

ref(1)

Figure 7. Typical Application (Switch Enable Control)

Bidirectional Translation

unidirectional or the outputs must be 3−stateable and be

controlled by some direction−control mechanism to prevent

HIGH−to−LOW contentions in either direction. If both

outputs are open−drain, no direction control is needed.

For the bidirectional clamping configuration (higher

voltage to lower voltage or lower voltage to higher voltage),

the EN input must be connected to VREF2 and both pins

pulled to HIGH side V

through a pull−up resistor

The reference supply voltage (V ) is connected to the

ref(1)

pu(D)

(typically 200 kW). This allows VREF2 to regulate the EN

processor core power supply voltage. When VREF2 is

connected through a 200 kW resistor to a 3.3 V to 5.5 V

input. A filter capacitor on VREF2 is recommended. The

I C−bus master output can be totem−pole or open−drain

pu(D)

power supply, and V

is set between 1.0 V and

ref(1)

(pull−up resistors may be required) and the I C−bus device

− 1 V), the output of each SCL1 and SDA1 has a

pu(D)

output can be totem−pole or open−drain (pull−up resistors

are required to pull the SCL2 and SDA2 outputs to Vpu(D)).

However, if either output is totem−pole, data must be

maximum output voltage equal to VREF1, and the output of

each SCL2 and SDA2 has a maximum output voltage equal

to V

pu(D)

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PCA9306

Table 8. APPLICATION OPERATING CONDITIONS Refer to Figure 6.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Reference Bias Voltage (2)

EN Pin Input Voltage

Reference Voltage (1)

Pass Switch Current

Reference Current

+ 0.6

2.1

1.5

bias(ref)(2)

ref(1)

+ 0.6

I(EN)

ref(1)

4.4

°C

sw(pass)

ref

Transistor

Operating in free−air

amb

Ambient Temperature

−55

+125

11. All typical values are at T

= 25 °C.

amb

Sizing Pull−up Resistor

The following table summarizes resistor reference

voltages and currents at 15 mA, 10 mA, and 3 mA. The

resistor values shown in the +10% column or a larger value

should be used to ensure that the pass voltage of the

transistor would be 350 mV or less. The external driver must

be able to sink the total current from the resistors on both

sides of the PCA9306 device at 0.175 V, although the 15 mA

only applies to current flowing through the PCA9306

device.

The pull−up resistor value needs to limit the current

through the pass transistor when it is in the ON state to about

15 mA. This ensures a pass voltage of 260 mV to 350 mV.

If the current through the pass transistor is higher than

15 mA, the pass voltage also is higher in the ON state. To set

the current through each pass transistor at 15 mA, the

pull−up resistor value is calculated as:

V_PU(D)* 0.35 V

(eq. 1)

R_PU

0.015 A

Table 9. PULLUP RESISTOR VALUES Calculated for V = 0.35 V; assumes output driver V = 0.175 V at stated current.

Pullup Resistor Value (W)

15 mA

+10% (Note 12)

10 mA

3 mA

+10% (Note 12)

(1)

Nominal

310

197

143

Nominal

465

+10%

512

325

237

160

127

Nominal

1550

983

pu(D)

5 V

341

217

158

106

1705

1082

788

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

295

215

717

145

483

532

115

383

422

283

312

12.+10% to compensate for V range and resistor tolerance.

Maximum Frequency Calculation

resistor is needed on the 3.3 V side. The capacitance and line

length of concern is on the 1.8 V side since it is driven

through the ON resistance of the PCA9306. If the line length

on the 1.8 V side is long enough there can be a reflection at

the chip/terminating end of the wire when the transition time

is shorter than the time of flight of the wire because the

PCA9306 looks like a high−impedance compared to the

wire. If the wire is not too long and the lumped capacitance

is not excessive the signal will only be slightly degraded by

the series resistance added by passing through the PCA9306.

If the lumped capacitance is large the rise time will

deteriorate, the fall time is much less affected and if the rise

time is slowed down too much the duty cycle of the clock

will be degraded and at some point the clock will no longer

be useful. So the principle design consideration is to

minimize the wire length and the capacitance on the 1.8 V

side for the clock path. A pull−up resistor on the 1.8 V side

can also be used to trade a slower fall time for a faster rise

time and can also reduce the overshoot in some cases.

The maximum frequency is totally dependent upon the

specifics of the application and the device can operate >

33 MHz. Basically, the PCA9306 behaves like a wire with

the additional characteristics of transistor device physics

and should be capable of performing at higher frequencies

if used correctly.

Here are some guidelines to follow that will help

maximize the performance of the device:

• Keep trace length to a minimum by placing the

PCA9306 close to the processor.

• The trace length should be less than half the time of

flight to reduce ringing and reflections.

• The faster the edge of the signal, the higher the chance

for ringing.

• The higher the drive strength (up to 15 mA), the higher

the frequency the device can use.

In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side

is being driven by a totem pole type driver no pull−up

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

US8

CASE 493

ISSUE F

DATE 01 SEP 2021

SCALE 4 :1

GENERIC

MARKING DIAGRAM*

XX MG

= Specific Device Code

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON04475D

US8

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

UDFN8, 1.45x1, 0.35P

CASE 517BZ−01

ISSUE O

SCALE 4:1

DATE 18 MAY 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. PACKAGE DIMENSIONS EXCLUSIVE OF

BURRS AND MOLD FLASH.

PIN ONE

REFERENCE

0.10

MILLIMETERS

DIM MIN

MAX

0.55

0.05

0.45

0.00

0.13 REF

0.10

TOP VIEW

SIDE VIEW

0.15

0.25

0.05

1.45 BSC

1.00 BSC

0.35 BSC

0.25

0.30

0.35

0.40

0.05

GENERIC

MARKING DIAGRAM*

SEATING

PLANE

e/2

X M

7X L

= Specific Device Code

M = Date Code

*This information is generic. Please refer

to device data sheet for actual part

marking.

8X b

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

0.10

A B

RECOMMENDED

SOLDERING FOOTPRINT*

NOTE 3

0.05

BOTTOM VIEW

0.48

0.22

1.18

0.53

0.35

PKG

PITCH

OUTLINE

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON56796E

UDFN8, 1.45X1, 0.35P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

UQFN8, 1.6x1.6, 0.5P

CASE 523AN−01

ISSUE O

DATE 26 NOV 2008

SCALE 4:1

NOTES:

MOLD CMPD

EXPOSED Cu

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND

0.30 mm FROM THE TERMINAL TIP.

PIN ONE

REFERENCE

MILLIMETERS

0.10

DETAIL B

DIM MIN

0.45

A1 0.00

MAX

0.60

0.05

OPTIONAL

CONSTRUCTION

0.10

0.13 REF

0.15

0.25

TOP VIEW

1.60 BSC

0.50 BSC

(A3)

DETAIL B

L3 0.25

0.35

−−−

0.45

0.15

0.35

0.05

(0.15)

0.05

(0.10)

GENERIC

MARKING DIAGRAM*

SIDE VIEW

SEATING

DETAIL A

PLANE

OPTIONAL

CONSTRUCTION

XX MG

8X L

XX = Specific Device Code

= Date Code

= Pb−Free Package

DETAIL A

8X b

*This information is generic. Please refer

to device data sheet for actual part

marking.

0.10

0.05

A B

NOTE 3

BOTTOM VIEW

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

SOLDERING FOOTPRINT*

1.70

0.50

PITCH

0.35

1.70

0.25

0.53

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON36348E

8 PIN UQFN, 1.6X1.6, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP8, 4.4x3.0, 0.65P

CASE 948AL

ISSUE A

DATE 20 MAY 2022

GENERIC

MARKING DIAGRAM*

XXX

YWW

XXX = Specific Device Code

= Year

WW = Work Week

= Assembly Location

= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34428E

TSSOP8, 4.4X3.0, 0.65P

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

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

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