NSBC115EDXV6T5G [ONSEMI]

100mA, 50V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, LEAD FREE, PLASTIC, CASE 463A-01, 6 PIN;


型号：	NSBC115EDXV6T5G
厂家：	ONSEMI
描述：	100mA, 50V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, LEAD FREE, PLASTIC, CASE 463A-01, 6 PIN 开关光电二极管晶体管
文件：	总6页 (文件大小：125K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MUN5236DW1,

NSBC115EDXV6

Dual NPN Bias Resistor

Transistors

R1 = 100 kW, R2 = 100 kW

http://onsemi.com

PIN CONNECTIONS

(2)

NPN Transistors with Monolithic Bias

Resistor Network

(3)

(1)

This series of digital transistors is designed to replace a single

device and its external resistor bias network. The Bias Resistor

Transistor (BRT) contains a single transistor with a monolithic bias

network consisting of two resistors; a series base resistor and a

base-emitter resistor. The BRT eliminates these individual

components by integrating them into a single device. The use of a BRT

can reduce both system cost and board space.

Features

(4)

(5)

(6)

 Simplifies Circuit Design

 Reduces Board Space

 Reduces Component Count

MARKING DIAGRAMS

 S and NSV Prefix for Automotive and Other Applications

Requiring Unique Site and Control Change Requirements;

AEC-Q101 Qualified and PPAP Capable

SOT−363

CASE 419B

7N M G

 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS

Compliant

MAXIMUM RATINGS

(T = 25C, common for Q and Q , unless otherwise noted)

SOT−563

CASE 463A

7N M G

Rating

Symbol

Max

Unit

Vdc

Collector-Base Voltage

Collector-Emitter Voltage

CBO

CEO

Vdc

Specific Device Code

Date Code*

Pb-Free Package

Collector Current − Continuous

Input Forward Voltage

100

mAdc

Vdc

IN(fwd)

Input Reverse Voltage

Vdc

IN(rev)

(Note: Microdot may be in either location)

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

*Date Code orientation may vary depending

upon manufacturing location.

ORDERING INFORMATION

†

Device

MUN5236DW1T1G

NSBC115EDXV6T1G

Package

SOT−363

SOT−563

Shipping

3,000/Tape & Reel

4,000/Tape & Reel

†For information on tape and reel specifications, including part orientation and

tape sizes, please refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

 Semiconductor Components Industries, LLC, 2012

Publication Order Number:

September, 2012 − Rev. 0

DTC115ED/D

MUN5236DW1, NSBC115EDXV6

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

MUN5236DW1 (SOT−363) ONE JUNCTION HEATED

Total Device Dissipation

T = 25C

(Note 1)

(Note 2)

(Note 1)

(Note 2)

187

256

1.5

2.0

Derate above 25C

mW/C

Thermal Resistance,

Junction to Ambient

(Note 1)

(Note 2)

670

490

C/W

MUN5236DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)

Total Device Dissipation

T = 25C

(Note 1)

(Note 2)

(Note 1)

(Note 2)

250

385

2.0

3.0

Derate above 25C

mW/C

Thermal Resistance,

Junction to Ambient

C/W

C

(Note 1)

(Note 2)

493

325

Thermal Resistance,

Junction to Lead

(Note 1)

(Note 2)

188

208

Junction and Storage Temperature Range

NSBC115EDXV6 (SOT−563) ONE JUNCTION HEATED

Total Device Dissipation

T , T

−55 to +150

stg

T = 25C

(Note 1)

357

2.9

mW/C

Derate above 25C

Thermal Resistance,

Junction to Ambient

C/W

(Note 1)

350

NSBC115EDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)

Total Device Dissipation

T = 25C

(Note 1)

500

4.0

mW/C

Derate above 25C

Thermal Resistance,

Junction to Ambient

C/W

C

(Note 1)

250

Junction and Storage Temperature Range

T , T

−55 to +150

stg

1. FR−4 @ Minimum Pad.

2. FR−4 @ 1.0  1.0 Inch Pad.

3. Both junction heated values assume total power is sum of two equally powered channels.

http://onsemi.com

MUN5236DW1, NSBC115EDXV6

ELECTRICAL CHARACTERISTICS (T = 25C, common for Q and Q , unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Collector-Base Cutoff Current

nAdc

mAdc

Vdc

CBO

(V = 50 V, I = 0)

−

100

500

0.05

−

Collector-Emitter Cutoff Current

(V = 50 V, I = 0)

CEO

Emitter-Base Cutoff Current

(V = 6.0 V, I = 0)

EBO

−

Collector-Base Breakdown Voltage

(I = 10 mA, I = 0)

(BR)CBO

(BR)CEO

Collector-Emitter Breakdown Voltage (Note 4)

(I = 2.0 mA, I = 0)

Vdc

−

ON CHARACTERISTICS

DC Current Gain (Note 4)

(I = 5.0 mA, V = 10 V)

−

150

−

0.25

−

Collector-Emitter Saturation Voltage (Note 4)

(I = 10 mA, I = 0.3 mA)

CE(sat)

Input Voltage (Off)

(V = 5.0 V, I = 100 mA)

Vdc

i(off)

i(on)

−

1.2

1.7

−

Input Voltage (On)

(V = 0.2 V, I = 1.0 mA)

−

Output Voltage (On)

(V = 5.0 V, V = 5.5 V, R = 1.0 kW)

−

0.2

Output Voltage (Off)

(V = 5.0 V, V = 0.25 V, R = 1.0 kW)

4.9

−

Input Resistor

Resistor Ratio

R /R

100

1.0

130

1.2

0.8

4. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle  2%.

400

350

300

250

(1) SOT−363; 1.0  1.0 Inch Pad

(2) SOT−563; Minimum Pad

200

(1) (2)

150

100

−50 −25

100

125 150

AMBIENT TEMPERATURE (C)

Figure 1. Derating Curve

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MUN5236DW1, NSBC115EDXV6

TYPICAL CHARACTERISTICS

MUN5236DW1, NSBC115EDXV6

1000

= 10 V

I /I = 10

T = −25C

75C

25C

75C

T = −25C

0.1

100

0.01

0.1

100

I , COLLECTOR CURRENT (mA)

Figure 2. V_CE(sat)vs. I_C

Figure 3. DC Current Gain

100

3.6

3.2

75C

f = 10 kHz

= 0 A

T = 25C

T = −25C

2.8

2.4

2.0

1.6

1.2

0.8

25C

= 5 V

0.4

0.1

V , REVERSE VOLTAGE (V)

V , INPUT VOLTAGE (V)

Figure 4. Output Capacitance

Figure 5. Output Current vs. Input Voltage

100

25C

75C

= 0.2 V

T = −25C

0.1

I , COLLECTOR CURRENT (mA)

Figure 6. Input Voltage vs. Output Current

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MUN5236DW1, NSBC115EDXV6

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE W

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.

MILLIMETERS

DIM MIN NOM MAX

0.80

INCHES

NOM MAX

1.10 0.031 0.037 0.043

0.10 0.000 0.002 0.004

0.008 REF

MIN

0.95

0.05

A1 0.00

−E−

0.20 REF

0.21

0.14

2.00

1.25

0.10

1.80

1.15

0.30 0.004 0.008 0.012

0.25 0.004 0.005 0.010

2.20 0.070 0.078 0.086

1.35 0.045 0.049 0.053

0.026 BSC

0.30 0.004 0.008 0.012

2.20 0.078 0.082 0.086

0.65 BSC

b 6 PL

0.10

2.00

0.20

2.10

0.2 (0.008)

SOLDERING FOOTPRINT*

0.50

0.0197

0.65

0.025

0.65

0.025

0.40

0.0157

1.9

0.0748

inches

SCALE 20:1

SC−88/SC70−6/SOT−363

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

MUN5236DW1, NSBC115EDXV6

PACKAGE DIMENSIONS

SOT−563, 6 LEAD

CASE 463A

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−X−

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE MATERIAL.

MILLIMETERS

DIM MIN NOM MAX

INCHES

NOM MAX

−Y−

MIN

0.50

0.17

0.08

1.50

1.10

0.55

0.22

0.12

1.60

1.20

0.5 BSC

0.20

0.60 0.020 0.021 0.023

0.27 0.007 0.009 0.011

0.18 0.003 0.005 0.007

1.70 0.059 0.062 0.066

1.30 0.043 0.047 0.051

0.02 BSC

b 56 PL

0.08 (0.003)

X Y

0.10

1.50

0.30 0.004 0.008 0.012

1.70 0.059 0.062 0.066

1.60

SOLDERING FOOTPRINT*

0.3

0.0118

0.45

0.0177

1.0

0.0394

1.35

0.0531

0.5

0.0197 0.0197

inches

SCALE 20:1

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

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DTC115ED/D

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NSBC115EDXV6T5G [ONSEMI]

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