NSBC115TD [ONSEMI]
Dual NPN Bias Resistor Transistors;
| 型号： | NSBC115TD |
| 厂家： | 
ONSEMI |
| 描述： | Dual NPN Bias Resistor Transistors |
| 文件： | 总5页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NSBC115TD
Dual NPN Bias Resistor
Transistors
R1 = 100 kW, R2 = 8 kW
NPN Transistors with Monolithic Bias
Resistor Network
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MARKING
DIAGRAM
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
AFMG
SOT−963
CASE 527AD
G
1
AF
M
G
=
=
=
Specific Device Code
Date Code*
Pb−Free Package
Features
(Note: Microdot may be in either location)
• S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
*Date Code orientation may vary depending
upon manufacturing location.
• Simplifies Circuit Design
PIN CONNECTIONS
• Reduces Board Space
• Reduces Component Count
(3)
(2)
(1)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
R
1
R
2
MAXIMUM RATINGS
Q
1
(T = 25°C, common for Q1 and Q2, unless otherwise noted)
A
Rating
Collector−Base Voltage
Collector−Emitter Voltage
Collector Current − Continuous
Input Forward Voltage
Symbol
Max
50
Unit
Vdc
Q
2
V
CBO
CEO
R
2
R
1
V
50
Vdc
I
C
100
40
mAdc
Vdc
(4)
(5)
(6)
V
IN(fwd)
Input Reverse Voltage
V
IN(rev)
6
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
†
Device
Package
Shipping
NSBC115TDP6T5G
SOT−963
8,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
October, 2013 − Rev. 1
DTC115TD/D
NSBC115TD
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
NSBC115TDP6 (SOT−963) One Junction Heated
Total Device Dissipation
P
D
T = 25°C
(Note 1)
(Note 2)
(Note 1)
(Note 2)
231
269
1.9
2.2
mW
A
Derate above 25°C
mW/°C
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
R
540
464
°C/W
q
JA
NSBC115TDP6 (SOT−963) Both Junction Heated (Note 3)
Total Device Dissipation
P
D
T = 25°C
(Note 1)
(Note 2)
(Note 1)
(Note 2)
339
408
2.7
3.3
mW
A
Derate above 25°C
mW/°C
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
R
369
306
°C/W
°C
q
JA
Junction and Storage Temperature Range
T , T
J
−55 to +150
stg
2
2
1. FR−4 @ 100 mm , 1 oz. copper traces, still air.
2. FR−4 @ 500 mm , 1 oz. copper traces, still air.
3. Both junction heated values assume total power is sum of two equally powered channels.
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2
NSBC115TD
ELECTRICAL CHARACTERISTICS (T = 25°C, common for Q and Q , unless otherwise noted)
A
1
2
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Base Cutoff Current
I
I
nAdc
nAdc
mAdc
Vdc
CBO
(V = 50 V, I = 0)
−
−
−
−
−
−
−
100
500
0.1
−
CB
E
Collector−Emitter Cutoff Current
(V = 50 V, I = 0)
CEO
CE
B
Emitter−Base Cutoff Current
(V = 6.0 V, I = 0)
I
EBO
−
EB
C
Collector−Base Breakdown Voltage
(I = 10 mA, I = 0)
V
V
(BR)CBO
(BR)CEO
50
50
C
E
Collector−Emitter Breakdown Voltage (Note 4)
(I = 2.0 mA, I = 0)
Vdc
−
C
B
ON CHARACTERISTICS
DC Current Gain (Note 4)
h
FE
(I = 5.0 mA, V = 10 V)
160
−
350
−
−
0.25
−
C
CE
Collector−Emitter Saturation Voltage (Note 4)
(I = 10 mA, I = 5.0 mA)
V
Vdc
Vdc
Vdc
Vdc
Vdc
kW
CE(sat)
C
B
Input Voltage (off)
(V = 5.0 V, I = 100 mA)
V
V
i(off)
−
0.6
1.0
−
CE
C
Input Voltage (on)
(V = 0.2 V, I = 1.0 mA)
i(on)
−
−
CE
C
Output Voltage (on)
(V = 5.0 V, V = 2.5 V, R = 1.0 kW)
V
OL
−
0.2
CC
B
L
Output Voltage (off)
V
OH
(V = 5.0 V, V = 0.25 V, R = 1.0 kW)
4.9
70
−
−
100
−
−
130
−
CC
B
L
Input Resistor
Resistor Ratio
R1
R /R
1
2
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%.
250
200
(1)
2
(1) SOT−963; 100 mm , 1 oz. copper trace
150
100
50
0
−50 −25
0
25
50
75
100
125 150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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3
NSBC115TD
TYPICAL CHARACTERISTICS
NSBC115TDP6
10
1
1000
I /I = 10
C
B
150°C
25°C
150°C
25°C
−55°C
−55°C
100
10
0.1
V
CE
= 10 V
0.01
0
10
20
30
40
50
1
10
100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 2. VCE(sat) vs. IC
Figure 3. DC Current Gain
2.4
2.0
100
10
150°C
f = 10 kHz
= 0 A
T = 25°C
A
25°C
I
E
−55°C
1.6
1.2
0.8
1
0.1
0.4
0
V
O
= 5 V
24
0.01
0
10
20
30
40
50
0
4
8
12
16
20
28
V , REVERSE VOLTAGE (V)
R
V , INPUT VOLTAGE (V)
in
Figure 4. Output Capacitance
Figure 5. Output Current vs. Input Voltage
100
−55°C
10
25°C
150°C
1
V
O
= 0.2 V
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage vs. Output Current
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4
NSBC115TD
PACKAGE DIMENSIONS
SOT−963
CASE 527AD
ISSUE E
NOTES:
D
X
Y
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
6
5
4
3
H
E
E
1
2
MILLIMETERS
DIM MIN
NOM
0.37
0.15
0.12
1.00
0.80
0.35 BSC
1.00
0.19 REF
0.10
MAX
0.40
0.20
0.17
1.05
0.85
C
TOP VIEW
e
A
b
C
D
E
0.34
0.10
0.07
0.95
0.75
SIDE VIEW
6X
L
e
HE
0.95
0.05
1.05
0.15
L
L2
RECOMMENDED
MOUNTING FOOTPRINT
6X
b
6X
L2
6X
6X
0.08
X Y
0.35
0.20
BOTTOM VIEW
PACKAGE
OUTLINE
1.20
0.35
PITCH
DIMENSIONS: MILLIMETERS
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DTC115TD/D
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