NSPU3061N2T5G [ONSEMI]
6.3 V 单向浪涌保护器件;
| 型号： | NSPU3061N2T5G |
| 厂家： | 
ONSEMI |
| 描述： | 6.3 V 单向浪涌保护器件 |
| 文件： | 总7页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NSPU3061
6.3 V Unidirectional ESD
and Surge Protection
Device
The NSPU3061 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, high peak
pulse current handling capability and fast response time provide best
in class protection on designs that are exposed to ESD. Because of its
small size, it is suited for use in cellular phones, tablets, MP3 players,
digital cameras and many other portable applications where board
space comes at a premium.
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MARKING
DIAGRAM
X2DFN2
CASE 714AB
6 M
Features
• Low Clamping Voltage
• Low Leakage
• Small Body Outline: 1.0 mm x 0.6 mm
6
M
= Specific Device Code
= Date Code
• Protection for the Following IEC Standards:
IEC61000−4−2 Level 4: 30 kV Contact Discharge
IEC61000−4−5 (Lightning): 36 A (8/20 ms)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
CATHODE
2
ANODE
Typical Applications
ORDERING INFORMATION
• USB V
and CC Line Protection
BUS
†
• Microphone Line Protection
• GPIO Protection
Device
NSPU3061N2T5G
Package
Shipping
X2DFN2
(Pb−Free)
8000 / Tape &
Reel
Table 1. MAXIMUM RATINGS
Rating
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Symbol
Value
30
Unit
IEC 61000−4−2 (ESD)
Contact
Air
kV
30
Operating Junction Temperature Range
T
−65 to +
°C
°C
A
J
150
Storage Temperature Range
T
−65 to +
150
STG
Minimum Peak Pulse Current
I
PP
36
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
March, 2019 − Rev. 3
NSPU3061/D
NSPU3061
Table 2. ELECTRICAL CHARACTERISTICS
A
I
(T = 25°C unless otherwise noted)
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
Working Peak Reverse Voltage
V
C
V
V
RWM
BR RWM
V
I
V
F
R
T
I
R
Maximum Reverse Leakage Current @ V
RWM
I
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
PP
Uni−Directional Surge Protection
Table 3. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
6.3
9.5
1
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
6.4
6.9
V
T
Reverse Leakage Current
Clamping Voltage (Note 1)
I
R
V
RWM
= 6.3 V, I/O Pin to GND
0.02
mA
V
V
C
IEC61000−4−2, 8 kV Contact
See Figures 2 & 3
6.4
Clamping Voltage TLP
(Note 2)
V
C
I
PP
= 8 A IEC61000−4−2 Level 2 Equivalent
V
( 4 kV Contact, 8 kV Air)
I
PP
= 16 A IEC61000−4−2 Level 4 Equivalent
6.6
( 8 kV Contact, 15 kV Air)
Reverse Peak Pulse Current
I
IEC61000−4−5 (8x20 ms) per Figure 1
36
40
A
V
PP
Clamping Voltage 8x20 ms
Waveform per Figure 1
V
I
PP
I
PP
I
PP
= 20 A
= 30 A
= 36 A
6.6
7.3
7.7
8.0
9.0
9.7
C
Dynamic Resistance
Junction Capacitance
R
100 ns TLP
= 0 V, f = 1 MHz
0.025
90
W
DYN
C
V
110
pF
J
R
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see application note AND8307/D
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
20
t
r
PEAK VALUE I
@ 8 ms
RSM
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 1. 8 x 20 ms Pulse Waveform
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2
NSPU3061
TYPICAL CHARACTERISTICS
40
35
30
25
20
15
10
5
10
5
0
−5
−10
−15
−20
−25
0
−30
−35
−5
−20
0
20
40
60
80
100
120
140
−20
0
20
40
60
80
100 120 140
TIME (ns)
TIME (ns)
Figure 2. ESD Clamping Voltage
Positive 8 kV Contact per IEC61000−4−2
Figure 3. ESD Clamping Voltage
Negative 8 kV Contact per IEC61000−4−2
10
9
10
9
20
18
16
14
12
10
8
−20
−18
8
−16
−14
−12
−10
−8
8
7
7
6
6
5
5
4
4
6
3
−6
3
4
2
−4
2
2
1
0
10
−2
1
0
0
0
0
1
2
3
4
5
6
7
8
9
0
−1
−2
−3
−4
−5
−6
−7
−8
V
CTLP
(V)
V
CTLP
(V)
Figure 4. Positive TLP I−V Curve
Figure 5. Negative TLP I−V Curve
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
1
0
1
0
0
5
10
15
20
25
(A)
30
35
40
45
0
5
10
15 20
25 30 35 40 45
I (A)
PK
50
I
PK
Figure 6. Positive Clamping Voltage vs. Peak
Figure 7. Negative Clamping Voltage vs. Peak
Pulse Current (tp = 8/20 ms)
Pulse Current (tp = 8/20 ms)
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3
NSPU3061
TYPICAL CHARACTERISTICS
1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−09
1E−10
1E−11
1E−10
1E−11
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
V
R
(V)
V
R
(V)
Figure 8. Breakdown Voltage
Figure 9. Reverse Leakage Current
100
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
6
V
BIAS
(V)
Figure 10. Line Capacitance, f = 1 MHz
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4
NSPU3061
Transmission Line Pulse (TLP) Measurement
ESD Voltage Clamping
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 11. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 12 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
50 W Coax
Cable
L
Attenuator
S
IEC 61000−4−2 Spec.
÷
First Peak
Current
(A)
50 W Coax
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Cable
I
M
V
M
10 MW
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
DUT
V
C
22.5
30
12
16
Oscilloscope
Figure 11. Simplified Schematic of a Typical TLP
System
IEC61000−4−2 Waveform
I
peak
100%
90%
I @ 30 ns
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 13. IEC61000−4−2 Spec
Oscilloscope
DUT
ESD Gun
Figure 12. Comparison Between 8 kV IEC 61000−4−2
and 8 A and 16 A TLP Waveforms
50 W
50 W
Cable
Figure 14. Diagram of ESD Test Setup
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2DFN2 1.0x0.6, 0.65P
CASE 714AB
ISSUE B
DATE 21 NOV 2017
SCALE 8:1
NOTES:
0.10
C
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A B
E
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
PIN 1
INDICATOR
MILLIMETERS
DIM MIN
NOM MAX
A
A1
b
D
E
e
L
0.34
−−−
0.45
0.95
0.55
0.37
0.03
0.50
1.00
0.60
0.65 BSC
0.25
0.40
0.05
0.55
1.05
0.65
0.05
C
TOP VIEW
NOTE 3
A
0.10
0.10
C
0.20
0.30
C
GENERIC
MARKING DIAGRAM*
A1
SEATING
PLANE
C
SIDE VIEW
XX M
e
b
XX = Specific Device Code
e/2
M
0.05
C A B
M
= Date Code
1
RECOMMENDED
2X
L
0.05
SOLDER FOOTPRINT*
M
C A B
1.20
2X
BOTTOM VIEW
2X
0.47
0.60
PIN 1
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON98172F
X2DFN2 1.0X0.6, 0.65P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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