NTB60N06G [ONSEMI]
60 V, 60 A, N−Channel TO−220 and D2PAK; 60 V ， 60 A ， N沟道TO- 220和D2PAK
| 型号： | NTB60N06G |
| 厂家： | 
ONSEMI |
| 描述： | 60 V, 60 A, N−Channel TO−220 and D2PAK |
| 文件： | 总10页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTP60N06, NTB60N06
Power MOSFET
60 V, 60 A, N−Channel
TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
http://onsemi.com
60 VOLTS, 60 AMPERES
Features
RDS(on) = 14 mW
• Pb−Free Packages are Available
N−Channel
D
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
G
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
MARKING
DIAGRAMS
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
4
Drain−to−Source Voltage
V
60
60
DSS
DGR
Drain
Drain−to−Gate Voltage (R = 10 MW)
V
GS
4
Gate−to−Source Voltage
− Continuous
V
V
"20
"30
GS
GS
− Non−Repetitive (t v10 ms)
p
TO−220
CASE 221A
STYLE 5
NTx60N06
Drain Current
− Continuous @ T = 25°C
AYWW
I
D
60
42.3
180
Adc
Apk
A
− Continuous @ T = 100°C
I
D
A
− Single Pulse (t v10 ms)
I
DM
p
1
Gate
3
1
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
150
1.0
2.4
W
W/°C
W
2
A
Source
3
2
Total Power Dissipation @ T = 25°C (Note 1)
A
Drain
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
T , T
−55 to
+175
°C
J
stg
4
Drain
E
AS
454
mJ
4
Energy − Starting T = 25°C
J
2
D PAK
NTx60N06
AYWW
(V = 75 Vdc, V = 10 Vdc, L = 0.3 mH
DD
GS
CASE 418B
STYLE 2
I
= 55 A, V = 60 Vdc)
2
L(pk)
DS
Thermal Resistance
− Junction−to−Case
°C/W
°C
3
R
R
1.0
62.5
q
JC
JA
2
1
Gate
3
− Junction−to−Ambient (Note 1)
q
Drain
Source
Maximum Lead Temperature for Soldering
T
260
L
Purposes, 1/8″ from case for 10 seconds
NTx60N06 = Device Code
x
A
Y
WW
= P or B
= Assembly Location
= Year
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
= Work Week
1. When surface mounted to an FR4 board using minimum recommended pad
ORDERING INFORMATION
See detailed ordering and shipping information in the package
2
size, (Cu Area 0.412 in ).
dimensions section on page 7 of this data sheet.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 3
NTP60N06/D
NTP60N06, NTB60N06
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(V = 0 Vdc, I = 250 mAdc)
V
Vdc
(BR)DSS
60
−
72.3
69.8
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V = ±20 Vdc, V = 0 Vdc)
I
−
−
±100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(V = V , I = 250 mAdc)
V
GS(th)
2.0
−
2.85
8.0
4.0
−
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 2)
R
V
DS(on)
(V = 10 Vdc, I = 30 Adc)
−
11.5
14
GS
D
Static Drain−to−Source On−Voltage (Note 2)
(V = 10 Vdc, I = 60 Adc)
Vdc
DS(on)
−
−
0.715
1.43
1.01
−
GS
D
(V = 10 Vdc, I = 30 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 2) (V = 8.0 Vdc, I = 12 Adc)
g
FS
−
35
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
2300
660
3220
925
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
144
300
rss
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
t
−
−
−
−
−
−
−
25.5
180.7
94.5
142.5
62
50
360
200
300
81
ns
d(on)
Rise Time
t
r
(V = 30 Vdc, I = 60 Adc,
DD
D
V
= 10 Vdc, R = 9.1 W) (Note 2)
G
GS
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
Gate Charge
Q
T
Q
1
Q
2
nC
(V = 48 Vdc, I = 60 Adc,
DS
D
10.8
29.4
−
V
GS
= 10 Vdc) (Note 2)
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 60 Adc, V = 0 Vdc) (Note 2)
V
SD
−
−
0.99
0.87
1.05
−
Vdc
ns
S
GS
(I = 45 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
64.9
44.1
−
−
−
−
(I = 60 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 2)
S
t
b
20.8
Reverse Recovery Stored Charge
Q
0.146
mC
RR
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTP60N06, NTB60N06
120
120
100
80
60
40
20
0
V
= 10 V
GS
7 V
V
DS
≥ 10 V
100
80
9 V
8 V
6 V
60
5.5 V
40
5 V
T = 25°C
J
20
0
T = 100°C
J
4.5 V
T = −55°C
J
0
1
2
3
4
5
3
4
5
6
7
8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.026
0.022
0.026
0.022
V
DS
= 10 V
V
GS
= 15 V
T = 100°C
J
T = 100°C
0.018
0.014
0.01
0.018
0.014
0.01
J
T = 25°C
J
T = 25°C
J
T = −55°C
J
T = −55°C
J
0.006
0.006
0
20
40
60
80
100
120
0
20
40
60
80
100
120
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Gate−to−Source
Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.2
2
10,000
1000
V
GS
= 0 V
I
V
= 30 A
D
= 10 V
T = 150°C
GS
J
1.8
1.6
1.4
1.2
1
T = 125°C
J
100
10
T = 100°C
J
0.8
0.6
0
10
20
30
40
50
60
−50 −25
0
25
50
75 100 125 150 175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
3
NTP60N06, NTB60N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
6400
5600
4800
4000
3200
2400
1600
V
= 0 V
V
GS
= 0 V
DS
T = 25°C
J
C
C
iss
rss
C
iss
C
oss
800
C
rss
0
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
4
NTP60N06, NTB60N06
1000
12
10
8
V
= 30 V
= 60 A
= 10 V
DS
I
D
Q
T
V
GS
V
GS
t
t
r
Q
1
Q
2
f
6
100
t
t
d(off)
4
2
I
= 60 A
D
d(on)
T = 25°C
J
10
0
0
10
20
30
40
50
60
70
1
10
R , GATE RESISTANCE (W)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
60
V
= 0 V
GS
50
40
30
20
T = 25°C
J
T = 150°C
J
T = 25°C
J
10
0
0.4
0.48
0.56
0.64
0.72
0.8
0.88
0.96
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
exceed (T
− T )/(R ).
currents below rated continuous I can safely be assumed to
J(MAX)
C
qJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
equal the values indicated.
http://onsemi.com
5
NTP60N06, NTB60N06
SAFE OPERATING AREA
1000
100
10
500
V
= 20 V
I
D
= 55 A
GS
10 ms
SINGLE PULSE
= 25°C
400
T
C
300
200
100 ms
1 ms
10 ms
100
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
dc
1
0
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
0.02
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
1
1
0.01
SINGLE PULSE
t
2
T
J(pk)
− T = P
R
q
(t)
JC
C
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
0.1
1.0
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
http://onsemi.com
6
NTP60N06, NTB60N06
ORDERING INFORMATION
Device
†
Package
Shipping
NTP60N06
TO−220
50 Units/Rail
50 Units/Rail
NTP60N06G
TO−220
(Pb−Free)
2
NTB60N06
D PAK
50 Units/Rail
50 Units/Rail
2
NTB60N06G
D PAK
(Pb−Free)
2
NTB60N06T4
D PAK
800 Tape & Reel
800 Tape & Reel
2
NTB60N06T4G
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
7
NTP60N06, NTB60N06
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
1
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
http://onsemi.com
8
NTP60N06, NTB60N06
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
A
4.83
0.89
1.40
8.89
S
1
2
3
2.54 BSC
−T−
SEATING
PLANE
K
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
W
J
G
K
L
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
H
M
N
P
R
S
V
D 3 PL
M
M
T B
0.13 (0.005)
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
NTP60N06, NTB60N06
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTP60N06/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明