NTD18N06T4G [ONSEMI]
功率 MOSFET，60V，18A，60mΩ，单 N 沟道，DPAK;
| 型号： | NTD18N06T4G |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，60V，18A，60mΩ，单 N 沟道，DPAK 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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NTD18N06
Power MOSFET
18 Amps, 60 Volts
N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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V
R
TYP
I
D
MAX
(BR)DSS
DS(on)
Features
60 V
51 mW
18 A
• Pb−Free Packages are Available
N−Channel
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
D
G
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
S
J
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
V
60
60
Vdc
Vdc
Vdc
MARKING
DIAGRAMS
DSS
Drain−to−Gate Voltage (R = 10 MW)
V
DGR
GS
Gate−to−Source Voltage
− Continuous
4
V
V
"20
"30
Drain
GS
GS
− Non−repetitive (t v10 ms)
p
4
Drain Current
DPAK
− Continuous @ T = 25°C
I
18
10
54
Adc
Apk
CASE 369C
STYLE 2
A
D
2
1
− Continuous @ T = 100°C
I
D
A
3
− Single Pulse (t v10 ms)
I
p
DM
2
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
55
0.36
2.1
W
W/°C
W
A
1
Gate
3
Drain
Source
Total Power Dissipation @ T = 25°C (Note 2)
A
4
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
J
stg
Drain
4
Single Pulse Drain−to−Source Avalanche
E
AS
72
mJ
DPAK−3
CASE 369D
STYLE 2
Energy − Starting T = 25°C
J
(V = 50 Vdc, V = 5.0 Vdc,
DD
GS
L = 1.0 mH, I (pk) = 12 A, V = 60 Vdc)
L
DS
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
°C/W
1
2
R
R
R
2.73
100
71.4
q
JC
JA
JA
3
q
q
1
2
3
Gate Drain Source
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
L
18N06 = Device Code
Y
WW
G
= Year
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recom-
mended Operating Conditions is not implied. Extended exposure to stresses
above the Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR−4 board using the minimum recommended
pad size.
= Work Week
= Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 2
NTD18N06/D
NTD18N06
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
V
(BR)DSS
(V = 0 Vdc, I = 250 mAdc)
60
−
70.8
68.8
−
−
Vdc
mV/°C
GS
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
mAdc
DSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
20 Vdc, V = 0 Vdc)
I
−
−
100
nAdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
GS(th)
(V = V , I = 250 mAdc)
2.0
−
3.1
7.0
4.0
−
Vdc
mV/°C
DS
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
R
V
mW
DS(on)
(V = 10 Vdc, I = 9.0 Adc)
−
51
60
GS
D
Static Drain−to−Source On−Resistance (Note 3)
(V = 10 Vdc, I = 18 Adc)
Vdc
DS(on)
−
−
0.91
0.85
1.3
−
GS
D
(V = 10 Vdc, I = 9.0 Adc, T = 150°C)
GS
D
J
Forward Transconductance (Note 3) (V = 7.0 Vdc, I = 9.0 Adc)
g
FS
−
10.1
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
509
162
47
710
230
100
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
−
−
−
−
−
−
−
12
23
25
50
40
40
30
−
ns
d(on)
(V = 30 Vdc, I = 18 Adc,
DD
Rise Time
t
r
D
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
19
R
= 9.1 W) (Note 3)
d(off)
G
t
f
20
Gate Charge
Q
T
Q
1
Q
2
15.3
3.2
7.3
nC
(V = 48 Vdc, I = 18 Adc,
DS
D
V
= 10 Vdc) (Note 3)
GS
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 18 Adc, V = 0 Vdc) (Note 3)
V
SD
−
−
0.98
0.87
1.15
Vdc
ns
S
GS
(I = 18 Adc, V = 0 Vdc, T = 150°C)
−
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
42
31
−
−
−
−
(I = 18 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 3)
S
t
b
11
Reverse Recovery Stored Charge
Q
0.066
mC
RR
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD18N06
40
30
20
10
40
30
V
≥ 10 V
DS
V
= 10 V
GS
7 V
9 V
8 V
6.5 V
6 V
20
10
0
5.5 V
5 V
T = 25°C
J
T = 100°C
J
T = −55°C
J
0
0
1
2
3
4
3
3.8
4.6
5.4
6.2
7
7.8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.12
0.1
0.12
0.1
V
GS
= 10 V
V
GS
= 15 V
T = 100°C
J
T = 100°C
J
0.08
0.08
T = 25°C
J
0.06
0.04
0.02
0.06
0.04
0.02
0
T = 25°C
J
T = −55°C
J
T = −55°C
J
0
0
10
20
30
40
0
10
20
30
40
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
100
10
2
1.8
1.6
1.4
1.2
1
V = 0 V
GS
I
V
= 9 A
D
= 10 V
GS
T = 150°C
J
T = 100°C
J
0.8
1
0.6
−50 −25
0
25
50
75 100 125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
versus Voltage
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3
NTD18N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1400
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
1200
1000
800
C
iss
C
rss
600
C
iss
400
C
oss
200
0
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTD18N06
1000
12
10
8
Q
T
V
GS
100
t
f
t
d(off)
Q
Q
2
1
6
t
r
4
10
1
t
d(on)
V
I
= 30 V
= 18 A
DS
2
0
I
= 18 A
D
D
V
GS
= 10 V
T = 25°C
J
0
4
8
12
16
1
10
R , GATE RESISTANCE (W)
100
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
20
V
GS
= 0 V
T = 25°C
J
16
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C
qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTD18N06
SAFE OPERATING AREA
100
10
80
V
= 20 V
I
D
= 12 A
GS
SINGLE PULSE
10 ms
T
C
= 25°C
60
100 ms
1 ms
40
10 ms
1
dc
20
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
J(pk)
− T = P
R
q
(t)
JC
C
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (ms)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
NTD18N06
ORDERING INFORMATION
Device
†
Package
Shipping
NTD18N06
DPAK
75 Units/Rail
75 Units/Rail
NTD18N06G
DPAK
(Pb−Free)
NTD18N06−1
DPAK−3
75 Units/Rail
75 Units/Rail
NTD18N06−1G
DPAK−3
(Pb−Free)
NTD18N06T4
DPAK
2500 Tape & Reel
2500 Tape & Reel
NTD18N06T4G
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NTD18N06
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
SEATING
PLANE
−T−
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
STYLE 2:
PIN 1. GATE
2. DRAIN
G
0.13 (0.005)
T
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
NTD18N06
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
NOTES:
C
B
R
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
S
E
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
4
2
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
2. DRAIN
G
M
T
0.13 (0.005)
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTD18N06/D
相关型号：
NTD20N03L271
TRANSISTOR 20 A, 30 V, 0.031 ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 369D-01, DPAK-3, FET General Purpose Power
ONSEMI
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