NTD20N06LT4G [ONSEMI]

Power MOSFET 20 Amps, 60 Volts Logic Level, NâChannel DPAK; 功率MOSFET 20安培， 60伏逻辑电平， NA ????频道DPAK


型号：	NTD20N06LT4G
厂家：	ONSEMI
描述：	Power MOSFET 20 Amps, 60 Volts Logic Level, NâChannel DPAK 功率MOSFET 20安培， 60伏逻辑电平， NA ????频道DPAK
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NTD20N06L, NTDV20N06L

Power MOSFET

20 Amps, 60 Volts

Logic Level, N−Channel DPAK

Designed for low voltage, high speed switching applications in

power supplies, converters and power motor controls and bridge

circuits.

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DS(on)

TYP

I MAX

(BR)DSS

Features

20 A

(Note 1)

60 V

39 mW@5.0 V

• AEC Q101 Qualified − NTDV20N06L

• These Devices are Pb−Free and are RoHS Compliant

N−Channel

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol Value

Unit

Vdc

MARKING DIAGRAMS

& PIN ASSIGNMENTS

Drain−to−Source Voltage

DSS

DGR

Drain−to−Gate Voltage (R = 10 MW)

Gate−to−Source Voltage

− Continuous

"15

"20

Drain

− Non−repetitive (t v10 ms)

DPAK

Drain Current

CASE 369C

(Surface Mount)

STYLE 2

− Continuous @ T = 25°C

Adc

Apk

− Continuous @ T = 100°C

− Single Pulse (t v10 ms)

Gate

Total Power Dissipation @ T = 25°C

W/°C

Drain

Derate above 25°C

Source

0.40

1.88

1.36

Total Power Dissipation @ T = 25°C (Note 1)

Total Power Dissipation @ T = 25°C (Note 2)

Operating and Storage Temperature Range

T , T

−55 to

+175

°C

Drain

stg

DPAK

CASE 369D

(Straight Lead)

STYLE 2

Single Pulse Drain−to−Source Avalanche

128

Energy − Starting T = 25°C

(V = 25 Vdc, V = 5.0 Vdc,

L = 1.0 mH, I (pk) = 16 A, V = 60 Vdc)

Thermal Resistance

°C/W

− Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

2.5

110

Gate Drain Source

Maximum Lead Temperature for Soldering

Purposes, 1/8 in from case for 10 seconds

260

°C

= Year

= Work Week

= Device Code

= Pb−Free Package

20N6L

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in ).

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

2. When surface mounted to an FR4 board using recommended pad size,

(Cu Area 0.412 in ).

Semiconductor Components Industries, LLC, 2011

Publication Order Number:

October, 2011 − Rev. 3

NTD20N06L/D

NTD20N06L, NTDV20N06L

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

(V = 0 Vdc, I = 250 mAdc)

Vdc

(BR)DSS

−

71.3

71.2

−

Temperature Coefficient (Positive)

mV/°C

mAdc

Zero Gate Voltage Drain Current

DSS

(V = 60 Vdc, V = 0 Vdc)

−

1.0

(V = 60 Vdc, V = 0 Vdc, T = 150°C)

Gate−Body Leakage Current (V

15 Vdc, V = 0 Vdc)

−

100

nAdc

Vdc

GSS

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

GS(th)

(V = V , I = 250 mAdc)

1.0

−

1.6

4.6

2.0

−

Threshold Temperature Coefficient (Negative)

mV/°C

Static Drain−to−Source On−Resistance (Note 3)

DS(on)

(V = 5.0 Vdc, I = 10 Adc)

−

Static Drain−to−Source On−Resistance (Note 3)

(V = 5.0 Vdc, I = 20 Adc)

DS(on)

Vdc

−

0.81

0.72

1.66

−

(V = 5.0 Vdc, I = 10 Adc, T = 150°C)

Forward Transconductance (Note 3) (V = 4.0 Vdc, I = 10 Adc)

−

17.5

−

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

iss

−

707

224

990

320

105

(V = 25 Vdc, V = 0 Vdc,

Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time

oss

f = 1.0 MHz)

rss

−

9.6

200

120

−

d(on)

(V = 30 Vdc, I = 20 Adc,

= 5.0 Vdc,

Turn−Off Delay Time

Fall Time

d(off)

= 9.1 W) (Note 3)

16.6

5.5

8.5

Gate Charge

(V = 48 Vdc, I = 20 Adc,

= 5.0 Vdc) (Note 3)

−

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage

(I = 20 Adc, V = 0 Vdc) (Note 3)

−

0.97

0.85

1.2

Vdc

(I = 20 Adc, V = 0 Vdc, T = 150°C)

−

Reverse Recovery Time

(I = 20 Adc, V = 0 Vdc,

dI /dt = 100 A/ms) (Note 3)

Reverse Recovery Stored Charge

0.066

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

ORDERING INFORMATION

†

Device

Package

Shipping

NTD20N06LG

DPAK

75 Units / Rail

(Pb−Free)

NTD20N06L−1G

NTD20N06LT4G

NTDV20N06LT4G

DPAK (Straight Lead)

(Pb−Free)

DPAK

(Pb−Free)

2500 / Tape & Reel

DPAK

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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NTD20N06L, NTDV20N06L

= 10 V

≥ 10 V

4.5 V

4 V

8 V

5 V

6 V

3.5 V

3 V

T = 25°C

T = 100°C

T = −55°C

1.6

2.4

3.2

4.8

5.6

V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V , GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

Figure 2. Transfer Characteristics

0.085

0.075

0.065

0.055

0.045

0.035

0.025

0.015

0.085

0.075

0.065

0.055

= 5 V

= 10 V

T = 100°C

T = 25°C

0.045

0.035

0.025

0.015

T = 25°C

T = −55°C

I , DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source Voltage

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10000

1000

1.8

1.6

= 0 V

= 10 A

= 5 V

T = 150°C

1.4

1.2

100

T = 100°C

0.8

0.6

−50 −25

75 100 125 150 175

T , JUNCTION TEMPERATURE (°C)

V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with

Figure 6. Drain−to−Source Leakage Current

Temperature

versus Voltage

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NTD20N06L, NTDV20N06L

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Dt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The capacitance (C ) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

iss

calculating t

and is read at a voltage corresponding to the

d(on)

on−state when calculating t

d(off)

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (I ) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a

resistive load, V remains virtually constant at a level

known as the plateau voltage, V . Therefore, rise and fall

SGP

times may be approximated by the following:

t = Q x R /(V − V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

R = the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R C In [V /(V − V )]

G iss GG GG GSP

d(on)

d(off)

= R C In (V /V )

GG GSP

iss

2400

= 0 V

T = 25°C

2000

1600

1200

800

iss

rss

iss

400

oss

rss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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NTD20N06L, NTDV20N06L

1000

= 30 V

= 20 A

= 5 V

100

d(off)

d(on)

= 20 A

T = 25°C

R , GATE RESISTANCE (OHMS)

100

Q , TOTAL GATE CHARGE (nC)

Figure 8. Gate−To−Source and Drain−To−Source

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

= 0 V

T = 25°C

0.6

0.68

0.76

0.84

0.92

V , SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non−linearly with an

increase of peak current in avalanche and peak junction

temperature.

junction temperature and a case temperature (T ) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance −

General Data and Its Use.”

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

current (I ), the energy rating is specified at rated

(I ) nor rated voltage (V ) is exceeded and the

continuous current (I ), in accordance with industry custom.

DSS

transition time (t ,t ) do not exceed 10 ms. In addition the total

power averaged over a complete switching cycle must not

The energy rating must be derated for temperature as shown

in the accompanying graph (Figure 12). Maximum energy at

r f

currents below rated continuous I can safely be assumed to

exceed (T

− T )/(R ).

J(MAX)

C qJC

equal the values indicated.

A Power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

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NTD20N06L, NTDV20N06L

SAFE OPERATING AREA

100

140

= 15 V

= 16 A

SINGLE PULSE

120

100

10 ms

= 25°C

100 ms

1 ms

10 ms

DS(on)

LIMIT

THERMAL LIMIT

PACKAGE LIMIT

0.1

100

125

150

175

V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

T , STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

1.0

D = 0.5

0.2

0.1

0.05

0.02

(pk)

0.1

(t) = r(t) R

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

0.01

SINGLE PULSE

− T = P

R (t)

J(pk)

(pk)

DUTY CYCLE, D = t /t

0.01

0.00001

0.0001

0.001

0.01

t, TIME (s)

0.1

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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NTD20N06L, NTDV20N06L

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

DETAIL A

INCHES

DIM MIN MAX

0.086 0.094

A1 0.000 0.005

0.025 0.035

MILLIMETERS

MIN

2.18

0.00

0.63

0.76

4.57

0.46

5.97

6.35

MAX

2.38

0.13

0.89

1.14

5.46

0.61

6.22

6.73

b2 0.030 0.045

b3 0.180 0.215

0.005 (0.13)

0.018 0.024

c2 0.018 0.024

GAUGE

SEATING

PLANE

0.235 0.245

0.250 0.265

0.090 BSC

2.29 BSC

9.40 10.41

1.40 1.78

2.74 REF

0.51 BSC

0.89 1.27

0.370 0.410

0.055 0.070

0.108 REF

0.020 BSC

DETAIL A

L3 0.035 0.050

ROTATED 905 CW

−−− 0.040

0.155 −−−

−−−

3.93

1.01

−−−

STYLE 2:

PIN 1. GATE

2. DRAIN

SOLDERING FOOTPRINT*

3. SOURCE

4. DRAIN

6.20

0.244

3.00

0.118

2.58

0.102

5.80

0.228

1.60

0.063

6.17

0.243

inches

SCALE 3:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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NTD20N06L, NTDV20N06L

PACKAGE DIMENSIONS

IPAK

CASE 369D−01

ISSUE C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

INCHES

DIM MIN MAX

MILLIMETERS

MIN

5.97

6.35

2.19

0.69

0.46

0.94

MAX

6.35

6.73

2.38

0.88

0.58

1.14

0.235 0.245

0.250 0.265

0.086 0.094

0.027 0.035

0.018 0.023

0.037 0.045

0.090 BSC

0.034 0.040

0.018 0.023

0.350 0.380

0.180 0.215

0.025 0.040

0.035 0.050

−T−

SEATING

PLANE

2.29 BSC

0.87

0.46

8.89

4.45

0.63

0.89

3.93

1.01

0.58

9.65

5.45

1.01

1.27

−−−

0.155

−−−

D 3 PL

STYLE 2:

PIN 1. GATE

2. DRAIN

0.13 (0.005)

3. SOURCE

4. DRAIN

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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NTD20N06L/D

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NTD20N06LT4G [ONSEMI]

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