NTD4810NHT4G [ONSEMI]
Power MOSFET 30 V, 54 A, Single N−Channel, DPAK/IPAK; 功率MOSFET的30 V ， 54 A单N沟道， DPAK / IPAK
| 型号： | NTD4810NHT4G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 30 V, 54 A, Single N−Channel, DPAK/IPAK |
| 文件： | 总8页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD4810NH
Power MOSFET
30 V, 54 A, Single N−Channel, DPAK/IPAK
Features
• Low R
to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
DS(on)
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• Optimized Gate Charge to Minimize Switching Losses
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
• Low R
G
10 mW @ 10 V
30 V
54 A
• These are Pb−Free Devices
16.7 mW @ 4.5 V
Applications
D
• CPU Power Delivery
• DC−DC Converters
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
N−Channel
J
G
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
30
Unit
V
V
DSS
S
4
V
GS
"20
10.8
8.4
V
Continuous Drain
I
D
A
T = 25°C
A
4
Current (R ) (Note 1)
q
JA
T = 85°C
A
4
Power Dissipation
(R ) (Note 1)
T = 25°C
P
2.0
W
A
A
D
q
JA
2
1
1
2
3
1
2
3
IPAK
CASE 369D
(Straight Lead
DPAK)
Continuous Drain
I
D
T = 25°C
A
8.6
6.7
3
Current (R ) (Note 2)
q
JA
T = 85°C
A
Steady
State
3 IPAK
CASE 369AC
(Straight Lead)
DPAK
Power Dissipation
(R ) (Note 2)
T = 25°C
A
P
I
1.28
W
A
CASE 369C
(Bent Lead)
STYLE 2
D
q
JA
Continuous Drain
T
C
T
C
T
C
= 25°C
= 85°C
= 25°C
54
42
50
D
Current (R
(Note 1)
)
q
JC
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Power Dissipation
(R ) (Note 1)
P
D
W
4
q
JC
Drain
4
4
Pulsed Drain Current
t =10ms T = 25°C
I
DM
120
45
A
A
p
A
Drain
Drain
Current Limited by Package
T = 25°C
A
I
DmaxPkg
Operating Junction and Storage Temperature
T , T
−55 to
175
°C
J
stg
Source Current (Body Diode)
Drain to Source dV/dt
I
41
6.0
66
A
S
2
dV/dt
V/ns
mJ
1
2
3
Drain
1
3
Gate Drain Source
Single Pulse Drain−to−Source Avalanche
E
AS
Gate Source
1
2
3
Energy (V = 24 V, V = 10 V,
DD
GS
Gate Drain Source
L = 0.3 mH, I
= 21 A, R = 25 W)
L(pk)
G
Y
WW
= Year
= Work Week
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
4810NH = Device Code
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 0
NTD4810NH/D
NTD4810NH
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case (Drain)
R
3.0
3.5
75
°C/W
q
JC
Junction−to−TAB (Drain)
R
q
JC−TAB
Junction−to−Ambient − Steady State (Note 1)
Junction−to−Ambient − Steady State (Note 2)
R
R
q
q
JA
JA
117
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
30
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
27
mV/°C
(BR)DSS
Zero Gate Voltage Drain Current
I
T = 25°C
1.0
10
mA
DSS
J
V
V
= 0 V,
= 24 V
GS
DS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V = "20 V
"100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.5
2.5
10
V
GS(TH)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
J
5.2
8.0
mV/°C
mW
GS(TH)
R
V
GS
= 10 to
11.5 V
I
D
I
D
I
D
I
D
= 30 A
= 15 A
= 30 A
= 15 A
DS(on)
7.8
V
GS
= 4.5 V
14.1
13.2
9.0
16.7
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
gFS
V
= 15 V, I = 15 A
S
DS
D
C
1225
280
145
8.9
pF
iss
V
= 0 V, f = 1.0 MHz,
GS
Output Capacitance
C
oss
V
DS
= 12 V
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
12
nC
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
2.5
G(TH)
V
= 4.5 V, V = 15 V,
DS
GS
I
D
= 30 A
Q
3.6
GS
GD
Q
3.9
Q
V
GS
= 11.5 V, V = 15 V,
22.5
nC
ns
G(TOT)
DS
I
D
= 30 A
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
t
10.6
19.2
11.7
3.6
d(on)
t
r
V
GS
= 4.5 V, V = 15 V,
DS
= 15 A, R = 3.0 W
G
I
D
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
Turn−On Delay Time
Rise Time
t
t
6.2
ns
d(on)
t
r
18
V
= 11.5 V, V = 15 V,
DS
= 15 A, R = 3.0 W
G
GS
I
D
Turn−Off Delay Time
Fall Time
18.5
2.2
d(off)
t
f
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4810NH
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T = 25°C
J
0.88
0.79
13.4
9.1
1.2
V
= 0 V,
GS
I
S
= 30 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
ta
V
GS
= 0 V, dIs/dt = 100 A/ms,
I
S
= 30 A
Discharge Time
tb
4.3
Reverse Recovery Time
PACKAGE PARASITIC VALUES
Source Inductance
Q
6.7
nC
nH
RR
L
2.49
0.0164
1.88
S
D
D
G
Drain Inductance, DPAK
Drain Inductance, IPAK
Gate Inductance
L
L
L
T = 25°C
A
3.46
Gate Resistance
R
0.75
W
G
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3
NTD4810NH
TYPICAL PERFORMANCE CURVES
60
70
10 V
8 V
6 V
4.5 V
V
DS
≥ 10 V
T = 25°C
J
60
50
40
30
20
4.2 V
4 V
5 V
50
40
30
20
3.8 V
T = 125°C
J
3.5 V
T = 25°C
J
10
0
3.2 V
3 V
10
0
T = −55°C
J
0
0.5
V
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
1
2
3
4
5
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.025
0.023
0.021
0.019
0.017
0.025
0.020
0.015
0.010
T = 25°C
J
I
= 30 A
D
T = 25°C
J
V
= 4.5 V
GS
0.015
0.013
0.011
V
GS
= 11.5 V
0.005
0
0.009
0.007
4
5
6
7
8
9
10
11
15
20
25
30
35
40
45
50
55
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
10,000
2.0
1.5
V
GS
= 0 V
I
V
= 30 A
D
= 10 V
GS
T = 150°C
J
1000
100
10
1.0
0.5
0
T = 125°C
J
−50 −25
0
25
50
75 100 125 150 175
4
8
12
16
20
24
28
32
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
NTD4810NH
TYPICAL PERFORMANCE CURVES
2000
1750
1500
1250
1000
750
15
20
16
V
DS
= 0 V
V
= 0 V
GS
T = 25°C
J
T = 25°C
J
12
Q
C
C
T
iss
C
iss
12
9
6
V
DS
V
GS
rss
8
4
0
Q
Q
2
1
500
3
0
C
oss
250
0
C
rss
15
10
5
0
5
10
15
20
25
30
0
2
4
6
8
10 12 14 16 18 20 22 24
V
GS
V
DS
Q , TOTAL GATE CHARGE (nC)
G
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
30
1000
V
I
= 15 V
= 30 A
= 11.5 V
V
= 0 V
DD
GS
D
T = 25°C
J
25
20
15
10
V
GS
100
t
r
t
f
t
d(off)
10
1
t
d(on)
5
0
1
10
R , GATE RESISTANCE (OHMS)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
SD
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
70
60
50
40
30
20
I
D
= 21 A
10 ms
100 ms
V
= 20 V
GS
1 ms
10 ms
dc
SINGLE PULSE
= 25°C
T
C
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
NTD4810NH
TYPICAL PERFORMANCE CURVES
100
10
25°C
100°C
125°C
1
0.1
1
10
100
1000
PULSE WIDTH (ms)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
J(pk)
− T = P
R
q
(t)
JC
C
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (ms)
1.0E−01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NTD4810NHT4G
DPAK
(Pb−Free)
2500 Tape & Reel
75 Units/Rail
NTD4810NH−1G
NTD4810NH−35G
IPAK
(Pb−Free)
IPAK Trimmed Lead
(3.5 " 0.15 mm)
(Pb−Free)
75 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NTD4810NH
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
B
R
C
V
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.09
A
B
C
D
E
F
G
H
J
K
R
V
W
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
A
K
SEATING PLANE
W
2.29 BSC
F
0.87
0.46
3.40
4.57
0.89
1.01
0.58
3.60
5.46
1.27
0.25
J
G
H
D 3 PL
0.000 0.010 0.000
0.13 (0.005) W
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7
NTD4810NH
PACKAGE DIMENSIONS
IPAK (STRAIGHT LEAD DPAK)
CASE 369D−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
R
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
4
2
Z
A
K
1
3
2.29 BSC
−T−
SEATING
PLANE
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
0.155
−−−
F
H
STYLE 2:
PIN 1. GATE
D 3 PL
2. DRAIN
3. SOURCE
4. DRAIN
G
M
T
0.13 (0.005)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NTD4810NH/D
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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