NTD4860N-1G [ONSEMI]

单 N 沟道,功率 MOSFET,25V,65A,7.5mΩ;
NTD4860N-1G
型号: NTD4860N-1G
厂家: ONSEMI    ONSEMI
描述:

单 N 沟道,功率 MOSFET,25V,65A,7.5mΩ

开关 脉冲 晶体管
文件: 总9页 (文件大小:198K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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NTD4860N  
MOSFET – Power, Single,  
N-Channel, DPAK/IPAK  
25 V, 65 A  
Features  
http://onsemi.com  
Trench Technology  
Low R  
Low Capacitance to Minimize Driver Losses  
Optimized Gate Charge to Minimize Switching Losses  
These are PbFree Devices  
to Minimize Conduction Losses  
DS(on)  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(ON)  
7.5 mW @ 10 V  
25 V  
65 A  
11.1 mW @ 4.5 V  
D
Applications  
VCORE Applications  
DCDC Converters  
High/Low Side Switching  
NChannel  
G
S
4
MAXIMUM RATINGS (T = 25°C unless otherwise stated)  
J
4
Parameter  
DraintoSource Voltage  
GatetoSource Voltage  
Symbol  
Value  
25  
Unit  
V
DSS  
V
V
A
4
V
GS  
20  
Continuous Drain  
Current R  
I
D
T = 25°C  
13  
A
1
2
3
2
1
1
2
3
q
JA  
3
T = 85°C  
A
10  
(Note 1)  
DPAK  
3 IPAK  
CASE 369AC  
(Straight Lead) (Straight Lead  
DPAK) STYLE 2  
IPAK  
CASE 369D  
Power Dissipation  
T = 25°C  
P
2.0  
W
A
A
D
CASE 369AA  
(Bent Lead)  
STYLE 2  
R
(Note 1)  
q
JA  
Continuous Drain  
Current R  
ID  
T = 25°C  
A
10.4  
8.0  
q
JA  
T = 85°C  
A
Steady  
State  
(Note 2)  
MARKING DIAGRAMS  
& PIN ASSIGNMENTS  
Power Dissipation  
T = 25°C  
A
P
I
1.28  
W
A
D
4
R
(Note 2)  
q
JA  
Drain  
4
4
Continuous Drain  
Current R  
T
C
T
C
T
C
= 25°C  
= 85°C  
= 25°C  
65  
50  
50  
D
Drain  
Drain  
q
JC  
(Note 1)  
Power Dissipation  
P
D
W
A
R
(Note 1)  
q
JC  
Pulsed Drain  
Current  
t =10ms  
p
T = 25°C  
A
I
DM  
130  
45  
2
1
2
3
Drain  
1
3
Gate Drain Source  
Current Limited by Package  
T = 25°C  
A
I
A
DmaxPkg  
Gate Source  
1
2
3
Gate Drain Source  
Operating Junction and Storage  
Temperature  
T ,  
55 to  
+175  
°C  
J
T
STG  
A
Y
WW  
= Assembly Location*  
= Year  
= Work Week  
Source Current (Body Diode)  
Drain to Source dV/dt  
I
S
42  
6
A
dV/dt  
EAS  
V/ns  
mJ  
4860N = Device Code  
Single Pulse DraintoSource Avalanche  
Energy (T = 25°C, V = 50 V, V = 10 V,  
84.5  
G
= PbFree Package  
J
DD  
GS  
* The Assembly Location code (A) is front side  
optional. In cases where the Assembly Location is  
stamped in the package, the front side assembly  
code may be blank.  
I = 13 A , L = 1.0 mH, R = 25 W)  
L
pk  
G
Lead Temperature for Soldering Purposes  
(1/8” from case for 10 s)  
T
260  
°C  
L
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
May, 2019 Rev. 2  
NTD4860N/D  
NTD4860N  
THERMAL RESISTANCE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
3
Unit  
JunctiontoCase (Drain)  
R
q
JC  
JunctiontoTAB (Drain)  
R
3.5  
75  
q
JCTAB  
°C/W  
JunctiontoAmbient – Steady State (Note 1)  
JunctiontoAmbient – Steady State (Note 2)  
R
R
q
q
JA  
JA  
117  
1. Surfacemounted on FR4 board using 1 sqin pad, 1 oz Cu.  
2. Surfacemounted on FR4 board using the minimum recommended pad size.  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
DraintoSource Breakdown Voltage  
V
V
GS  
= 0 V, I = 250 mA  
25  
V
(BR)DSS  
D
DraintoSource Breakdown Voltage  
Temperature Coefficient  
V
/
21  
(BR)DSS  
mV/°C  
T
J
Zero Gate Voltage Drain Current  
I
V
= 0 V,  
= 20 V  
T = 25°C  
1.0  
10  
DSS  
GS  
DS  
J
V
mA  
T = 125°C  
J
GatetoSource Leakage Current  
ON CHARACTERISTICS (Note 3)  
Gate Threshold Voltage  
I
V
= 0 V, V  
=
20 V  
100  
nA  
GSS  
DS  
GS  
V
V
= V , I = 250 mA  
1.45  
2.5  
V
GS(TH)  
GS  
DS  
D
Negative Threshold Temperature  
Coefficient  
V
/T  
5.2  
GS(TH)  
J
mV/°C  
DraintoSource On Resistance  
R
V
= 10 V  
I
I
= 30 A  
= 30 A  
6.1  
8.9  
48  
7.5  
DS(on)  
GS  
D
mW  
V
GS  
= 4.5 V  
11.1  
D
Forward Transconductance  
CHARGES AND CAPACITANCES  
Input Capacitance  
g
FS  
V
= 1.5 V, I = 15 A  
S
DS  
D
C
1308  
342  
169  
11  
ISS  
Output Capacitance  
C
C
V
GS  
= 0 V, f = 1.0 MHz, V = 12 V  
pF  
OSS  
RSS  
DS  
Reverse Transfer Capacitance  
Total Gate Charge  
Q
16.5  
G(TOT)  
Threshold Gate Charge  
GatetoSource Charge  
GatetoDrain Charge  
Total Gate Charge  
Q
1.2  
G(TH)  
V
= 4.5 V, V = 15 V, I = 30 A  
nC  
nC  
GS  
DS  
D
Q
3.9  
GS  
GD  
Q
4.7  
Q
t
V
GS  
= 10 V, V = 15 V, I = 30 A  
21.8  
G(TOT)  
DS  
D
SWITCHING CHARACTERISTICS (Note 4)  
TurnOn Delay Time  
12.2  
20.1  
15.2  
4.3  
d(ON)  
Rise Time  
t
r
V
= 4.5 V, V = 15 V,  
DS  
GS  
D
ns  
I
= 15 A, R = 3.0 W  
G
TurnOff Delay Time  
t
d(OFF)  
Fall Time  
t
f
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
3. Pulse Test: pulse width 300 ms, duty cycle 2%.  
4. Switching characteristics are independent of operating junction temperatures.  
http://onsemi.com  
2
 
NTD4860N  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified) (continued)  
J
Parameter  
SWITCHING CHARACTERISTICS (Note 4)  
TurnOn Delay Time  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
t
7.1  
17  
d(ON)  
Rise Time  
t
r
V
V
= 11.5 V, V = 15 V,  
DS  
GS  
D
ns  
I
= 15 A, R = 3.0 W  
G
TurnOff Delay Time  
t
22  
d(OFF)  
Fall Time  
t
f
2.3  
DRAINSOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
T = 25°C  
0.9  
0.76  
12.7  
7.0  
1.2  
SD  
RR  
J
= 0 V,  
= 30 A  
GS  
V
I
S
T = 125°C  
J
Reverse Recovery Time  
Charge Time  
t
t
a
ns  
V
= 0 V, dIS/dt = 100 A/ms,  
GS  
I
S
= 30 A  
Discharge Time  
t
b
5.7  
Reverse Recovery Charge  
PACKAGE PARASITIC VALUES  
Source Inductance  
Q
3.5  
nC  
RR  
L
L
L
2.49  
0.0164  
1.88  
S
D
D
G
Drain Inductance, DPAK  
Drain Inductance, IPAK  
Gate Inductance  
nH  
T = 25°C  
A
L
3.46  
Gate Resistance  
R
0.75  
W
G
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
3. Pulse Test: pulse width 300 ms, duty cycle 2%.  
4. Switching characteristics are independent of operating junction temperatures.  
http://onsemi.com  
3
 
NTD4860N  
TYPICAL PERFORMANCE CURVES  
60  
60  
50  
40  
30  
20  
10  
0
4 V  
10V  
V
DS  
10 V  
3.8 V  
3.6 V  
50  
40  
30  
20  
10  
0
T = 25°C  
J
3.4 V  
3.2 V  
T = 125°C  
J
3.0 V  
2.8 V  
T = 25°C  
J
T = 55°C  
J
0
1
2
3
4
5
0
1
2
3
4
5
V
DS  
, DRAINTOSOURCE VOLTAGE (VOLTS)  
V
GS  
, GATETOSOURCE VOLTAGE (VOLTS)  
Figure 1. OnRegion Characteristics  
Figure 2. Transfer Characteristics  
0.012  
0.040  
0.036  
0.032  
0.028  
0.024  
0.020  
0.016  
0.012  
0.008  
0.004  
T = 25°C  
J
I
= 30 A  
D
0.011  
0.010  
0.009  
0.008  
0.007  
0.006  
T = 25°C  
J
V
GS  
= 4.5 V  
V
GS  
= 11.5 V  
0.005  
0.004  
0
2
3
4
5
6
7
8
9
10  
11  
10  
20  
30  
40  
50  
60  
V
GS  
, GATETOSOURCE VOLTAGE (VOLTS)  
I , DRAIN CURRENT (AMPS)  
D
Figure 3. OnResistance vs. GatetoSource  
Figure 4. OnResistance vs. Drain Current and  
Voltage  
Gate Voltage  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
10000  
1000  
V
= 0 V  
GS  
I
V
= 30 A  
D
= 10 V  
GS  
T = 150°C  
J
T = 125°C  
J
100  
10  
50 25  
0
25  
50  
75 100 125 150 175  
2
4
6
8
10  
12  
14  
16  
18  
20  
T , JUNCTION TEMPERATURE (°C)  
J
V
DS  
, DRAINTOSOURCE VOLTAGE (VOLTS)  
Figure 5. OnResistance Variation with  
Figure 6. DraintoSource Leakage Current  
Temperature  
vs. Drain Voltage  
http://onsemi.com  
4
NTD4860N  
TYPICAL PERFORMANCE CURVES  
10  
2000  
1500  
1000  
500  
0
Q
V
= 0 V  
T
GS  
T = 25°C  
J
8
6
4
2
0
C
iss  
V
GS  
Q
Q
1
2
C
oss  
I
D
= 30 A  
C
rss  
T = 25°C  
J
0
5
10  
15  
20  
25  
0
5
10  
15  
20  
25  
DRAINTOSOURCE VOLTAGE (VOLTS)  
Q , TOTAL GATE CHARGE (nC)  
G
Figure 7. Capacitance Variation  
Figure 8. GateToSource and DrainToSource  
Voltage vs. Total Charge  
1000  
30  
V
DD  
= 15 V  
V
GS  
= 0 V  
I
V
= 15 A  
D
T = 25°C  
J
25  
20  
15  
10  
5
= 11.5 V  
GS  
100  
10  
1
t
d(off)  
t
r
t
d(on)  
t
f
0
1
10  
R , GATE RESISTANCE (OHMS)  
100  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
V
, SOURCETODRAIN VOLTAGE (VOLTS)  
G
SD  
Figure 9. Resistive Switching Time  
Variation vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
1000  
100  
10  
100  
90  
80  
70  
60  
50  
40  
30  
20  
I
= 13 A  
D
10 ms  
100 ms  
V
= 20 V  
1 ms  
GS  
SINGLE PULSE  
= 25°C  
10 ms  
dc  
T
C
1
R
LIMIT  
DS(on)  
THERMAL LIMIT  
PACKAGE LIMIT  
10  
0
0.1  
0.1  
1
10  
100  
25  
50  
75  
100  
125  
150  
175  
V
DS  
, DRAINTOSOURCE VOLTAGE (VOLTS)  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
Figure 12. Maximum Avalanche Energy vs.  
Starting Junction Temperature  
http://onsemi.com  
5
NTD4860N  
TYPICAL PERFORMANCE CURVES  
1.0  
D = 0.5  
0.2  
0.1  
0.05  
0.02  
P
(pk)  
0.1  
R
(t) = r(t) R  
q
JC  
q
JC  
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
READ TIME AT t  
0.01  
SINGLE PULSE  
t
1
1
t
2
T
J(pk)  
T = P  
R
q
JC  
(t)  
C
(pk)  
DUTY CYCLE, D = t /t  
1
2
0.01  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
t, TIME (ms)  
1.0E-01  
1.0E+00  
1.0E+01  
Figure 13. Thermal Response  
Package  
ORDERING INFORMATION  
Device  
Shipping  
NTD4860NT4G  
DPAK  
(PbFree)  
2500 / Tape & Reel  
NTD4860N1G  
NTD4860N35G  
IPAK  
75 Units / Rail  
75 Units / Rail  
(PbFree)  
IPAK Trimmed Lead  
(3.5 0.15 mm)  
(PbFree)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
6
NTD4860N  
PACKAGE DIMENSIONS  
DPAK (SINGLE GUAGE)  
CASE 369AA  
ISSUE B  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
2. CONTROLLING DIMENSION: INCHES.  
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-  
MENSIONS b3, L3 and Z.  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
FLASH, PROTRUSIONS, OR BURRS. MOLD  
FLASH, PROTRUSIONS, OR GATE BURRS SHALL  
NOT EXCEED 0.006 INCHES PER SIDE.  
5. DIMENSIONS D AND E ARE DETERMINED AT THE  
OUTERMOST EXTREMES OF THE PLASTIC BODY.  
6. DATUMS A AND B ARE DETERMINED AT DATUM  
PLANE H.  
C
A
D
A
E
c2  
b3  
B
4
2
L3  
L4  
Z
H
DETAIL A  
1
3
INCHES  
DIM MIN MAX  
0.086 0.094  
A1 0.000 0.005  
0.025 0.035  
MILLIMETERS  
MIN  
2.18  
0.00  
0.63  
0.76  
4.57  
0.46  
0.46  
5.97  
6.35  
MAX  
2.38  
0.13  
0.89  
1.14  
5.46  
0.61  
0.61  
6.22  
6.73  
A
b2  
c
b
b
b2 0.030 0.045  
b3 0.180 0.215  
M
0.005 (0.13)  
C
H
e
c
0.018 0.024  
c2 0.018 0.024  
GAUGE  
SEATING  
L2  
PLANE  
C
D
E
e
0.235 0.245  
0.250 0.265  
0.090 BSC  
PLANE  
2.29 BSC  
9.40 10.41  
1.40 1.78  
2.74 REF  
0.51 BSC  
0.89 1.27  
H
L
L1  
L2  
0.370 0.410  
0.055 0.070  
0.108 REF  
L
A1  
L1  
0.020 BSC  
DETAIL A  
L3 0.035 0.050  
ROTATED 905 CW  
L4  
Z
−−− 0.040  
0.155 −−−  
−−−  
3.93  
1.01  
−−−  
STYLE 2:  
PIN 1. GATE  
2. DRAIN  
SOLDERING FOOTPRINT*  
3. SOURCE  
4. DRAIN  
6.20  
0.244  
3.00  
0.118  
2.58  
0.102  
5.80  
0.228  
1.60  
0.063  
6.17  
0.243  
mm  
inches  
ǒ
Ǔ
SCALE 3:1  
*For additional information on our PbFree strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
7
NTD4860N  
PACKAGE DIMENSIONS  
3 IPAK, STRAIGHT LEAD  
CASE 369AC  
ISSUE O  
NOTES:  
1.. DIMENSIONING AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
2.. CONTROLLING DIMENSION: INCH.  
3. SEATING PLANE IS ON TOP OF  
DAMBAR POSITION.  
4. DIMENSION A DOES NOT INCLUDE  
DAMBAR POSITION OR MOLD GATE.  
B
R
C
V
E
INCHES  
DIM MIN MAX  
MILLIMETERS  
MIN  
5.97  
6.35  
2.19  
0.69  
0.46  
0.94  
MAX  
6.22  
6.73  
2.38  
0.88  
0.58  
1.09  
A
B
C
D
E
F
G
H
J
K
R
V
W
0.235 0.245  
0.250 0.265  
0.086 0.094  
0.027 0.035  
0.018 0.023  
0.037 0.043  
0.090 BSC  
0.034 0.040  
0.018 0.023  
0.134 0.142  
0.180 0.215  
0.035 0.050  
A
K
SEATING PLANE  
W
2.29 BSC  
F
0.87  
0.46  
3.40  
4.57  
0.89  
1.01  
0.58  
3.60  
5.46  
1.27  
0.25  
J
G
H
D 3 PL  
0.000 0.010 0.000  
0.13 (0.005) W  
IPAK  
CASE 369D  
ISSUE C  
C
B
R
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
V
E
2. CONTROLLING DIMENSION: INCH.  
INCHES  
DIM MIN MAX  
MILLIMETERS  
4
2
MIN  
5.97  
6.35  
2.19  
0.69  
0.46  
0.94  
MAX  
6.35  
6.73  
2.38  
0.88  
0.58  
1.14  
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245  
0.250 0.265  
0.086 0.094  
0.027 0.035  
0.018 0.023  
0.037 0.045  
0.090 BSC  
0.034 0.040  
0.018 0.023  
0.350 0.380  
0.180 0.215  
0.025 0.040  
0.035 0.050  
A
K
S
1
3
T−  
SEATING  
PLANE  
2.29 BSC  
0.87  
0.46  
8.89  
4.45  
0.63  
0.89  
3.93  
1.01  
0.58  
9.65  
5.45  
1.01  
1.27  
−−−  
J
F
H
0.155  
−−−  
D 3 PL  
STYLE 2:  
PIN 1. GATE  
2. DRAIN  
G
M
T
0.13 (0.005)  
3. SOURCE  
4. DRAIN  
ON Semiconductor and the  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.  
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed  
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PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
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For additional information, please contact your local  
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NTD4860N/D  

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