NTD4906N [ONSEMI]
Power MOSFET 30 V, 54 A, Single N−Channel, DPAK/IPAK; 功率MOSFET的30 V ， 54 A单N沟道， DPAK / IPAK
| 型号： | NTD4906N |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 30 V, 54 A, Single N−Channel, DPAK/IPAK |
| 文件： | 总8页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD4906N
Power MOSFET
30 V, 54 A, Single N−Channel, DPAK/IPAK
Features
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• These are Pb−Free Devices
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V
R
MAX
I MAX
D
(BR)DSS
DS(on)
Applications
5.5 mW @ 10 V
8.0 mW @ 4.5 V
• CPU Power Delivery
• DC−DC Converters
30 V
54 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Symbol
Value
30
Unit
V
V
DSS
N−Channel
V
GS
"20
14
V
G
I
D
A
T = 25°C
A
Current (R
(Note 1)
)
q
JA
T = 100°C
A
9.9
2.6
S
4
Power Dissipation
(R ) (Note 1)
T = 25°C
A
P
W
A
D
D
D
4
q
JA
4
Continuous Drain
I
D
T = 25°C
A
10.3
7.3
Current (R ) (Note
q
JA
T = 100°C
A
Steady
State
2)
2
1
1
2
3
3
1
2
3
CASE 369D
IPAK
(Straight Lead
DPAK)
Power Dissipation
(R ) (Note 2)
T = 25°C
A
P
I
1.38
W
A
q
JA
CASE 369AD
IPAK
(Straight Lead)
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
Continuous Drain
T
= 25°C
= 100°C
= 25°C
54
38
D
C
C
Current (R
(Note 1)
)
q
JC
T
C
Power Dissipation
(R ) (Note 1)
T
P
37.5
W
q
JC
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Pulsed Drain Current t =10ms T = 25°C
I
223
90
A
A
p
A
DM
I
DmaxPkg
4
Current Limited by Package
T = 25°C
A
Drain
4
4
Operating Junction and Storage Temperature
T , T
−55 to
175
°C
J
stg
Drain
Drain
Source Current (Body Diode)
Drain to Source dV/dt
I
32
6.5
48
A
S
dV/dt
V/ns
mJ
Single Pulse Drain−to−Source Avalanche
E
AS
Energy (T = 25°C, V = 50 V, V = 10 V,
J
DD
GS
2
1
2
3
L = 0.1 mH, I
= 31 A, R = 25 W)
Drain
L(pk)
G
1
3
Gate Drain Source
Gate Source
1
2
3
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Gate Drain Source
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Y
WW
= Year
= Work Week
4906N = Device Code
= Pb−Free Package
G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
June, 2009 − Rev. 1
NTD4906N/D
NTD4906N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case (Drain)
R
4.0
4.3
58
°C/W
q
JC
Junction−to−Tab (Drain)
R
q
JC−TAB
Junction−to−Ambient − Steady State (Note 1)
Junction−to−Ambient − Steady State (Note 2)
R
R
q
JA
JA
109
q
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
30
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
15
mV/°C
(BR)DSS
J
Zero Gate Voltage Drain Current
I
mA
T = 25°C
1.0
10
DSS
J
V
V
= 0 V,
= 24 V
GS
DS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V = "20 V
"100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.0
1.6
4.0
2.2
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
J
mV/°C
GS(TH)
Drain−to−Source On Resistance
R
V
= 10 V
GS
mW
I
D
I
D
I
D
I
D
= 30 A
= 15 A
= 30 A
= 15 A
4.6
4.6
6.5
6.5
52
5.5
8.0
DS(on)
V
GS
= 4.5 V
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
gFS
V
DS
= 1.5 V, I = 30 A
S
D
pF
C
iss
1932
642
19
V
= 0 V, f = 1.0 MHz,
GS
Output Capacitance
C
oss
V
DS
= 15 V
Reverse Transfer Capacitance
Total Gate Charge
C
rss
nC
Q
11
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
3.0
5.9
1.8
24
G(TH)
V
= 4.5 V, V = 15 V,
DS
GS
I
D
= 30 A
Q
GS
GD
Q
Q
V
= 10 V, V = 15 V,
nC
ns
G(TOT)
GS
DS
I
D
= 30 A
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
t
13
21
d(on)
t
r
V
GS
= 4.5 V, V = 15 V,
DS
I
= 15 A, R = 3.0 W
D
G
Turn−Off Delay Time
Fall Time
t
20
d(off)
t
f
3.7
7.7
19
ns
Turn−On Delay Time
Rise Time
t
t
d(on)
t
r
V
GS
= 10 V, V = 15 V,
DS
I
D
= 15 A, R = 3.0 W
G
Turn−Off Delay Time
Fall Time
22
d(off)
t
f
2.3
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4906N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T = 25°C
J
0.87
0.76
33
1.1
V
= 0 V,
GS
I
S
= 30 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
ta
17
V
GS
= 0 V, dIs/dt= 100 A/ms,
I
S
= 30 A
Discharge Time
tb
16
Reverse Recovery Time
PACKAGE PARASITIC VALUES
Source Inductance (Note 5)
Drain Inductance, DPAK
Drain Inductance, IPAK (Note 5)
Gate Inductance (Note 5)
Q
25
nC
nH
RR
L
2.85
0.0164
1.88
4.9
S
D
D
G
L
L
L
T = 25°C
A
Gate Resistance
R
G
1.0
2.0
W
5. Assume terminal length of 110 mils.
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3
NTD4906N
TYPICAL PERFORMANCE CURVES
100
125
7 V
4.5 V
10 V
4.2 V
V
DS
≥ 10 V
4 V
80
100
75
3.8 V
3.6 V
T = 125°C
J
60
40
3.4 V
3.2 V
3.0 V
2.8 V
T = 25°C
J
50
25
0
20
0
2.6 V
2.4 V
T = −55°C
J
0
1
2
3
4
5
2
2.5
3
3.5
4
4.5
5
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.010
0.009
0.008
0.007
0.006
0.010
0.009
0.008
0.007
0.006
0.005
0.004
T = 25°C
I
= 30 A
J
D
T = 25°C
J
V
= 4.5 V
GS
V
= 10 V
GS
0.005
0.004
3
4
5
6
7
8
9
10
15 25 35 45 55 65 75 85 95 105 115 125
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
10,000
1000
100
2.0
1.8
V
GS
= 0 V
I
V
= 30 A
D
= 10 V
GS
T = 150°C
J
1.6
1.4
T = 125°C
J
1.2
1.0
T = 85°C
J
0.8
0.6
10
−50 −25
0
25
50
75 100 125 150 175
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (°C)
J
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Drain Voltage
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4
NTD4906N
TYPICAL PERFORMANCE CURVES
2500
2000
1500
1000
15
T = 25°C
GS
J
V
= 0 V
12
9
Q
T
C
C
iss
V
GS
6
Q
oss
GD
Q
GS
V
V
= 15 V
= 10 V
= 30 A
DD
500
0
3
0
GS
I
D
C
rss
T = 25°C
J
0
5
10
15
20
25
30
0
5
10
15
20
25
30
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
25
20
15
10
1000
V
= 15 V
= 15 A
= 10 V
V
GS
= 0 V
DD
I
D
V
GS
t
d(off)
100
t
t
f
r
T = 125°C
J
t
d(on)
10
1
5
0
T = 25°C
J
1
10
100
0
0.2
0.4
0.6
0.8
1.0
R , GATE RESISTANCE (OHMS)
G
V , SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
50
45
40
35
I
D
= 31 A
10 ms
30
25
20
15
100 ms
V
= 20 V
1 ms
GS
SINGLE PULSE
= 25°C
10 ms
dc
T
C
1
R
LIMIT
DS(on)
10
THERMAL LIMIT
PACKAGE LIMIT
5
0
25
0.1
0.1
1
10
100
50
75
100
125
150
175
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
NTD4906N
TYPICAL PERFORMANCE CURVES
100
10
50% (DUTY CYCLE)
20%
10%
5.0%
2.0%
1.0
0.1
1.0%
SINGLE PULSE
0.01
PSi TAB-A
0.001
0.000001
0.00001
0.0001
0.001
0.01
PULSE TIME (s)
0.1
1.0
10
100
1000
Figure 13. FET Thermal Response
80
70
60
50
40
30
20
10
0
0
10
20
30
ID (A)
40
50
60
70
Figure 14. GFS vs ID
ORDERING INFORMATION
Order Number
†
Package
Shipping
NTD4906NT4G
DPAK
2500 / Tape & Reel
75 Units / Rail
(Pb−Free)
NTD4906N−1G
NTD4906N−35G
IPAK
(Pb−Free)
IPAK Trimmed Lead
75 Units / Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NTD4906N
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.63
0.46
0.77
MAX
6.22
6.73
2.38
0.89
0.61
1.14
A
B
C
D
E
F
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.030 0.045
0.386 0.410
0.018 0.023
0.090 BSC
4
2
Z
A
H
S
1
3
H
J
L
9.80 10.40
U
0.46
0.58
2.29 BSC
R
S
U
V
Z
0.180 0.215
0.024 0.040
4.57
0.60
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
F
J
0.020
0.035 0.050
0.155 −−−
−−−
L
D 2 PL
M
0.13 (0.005)
T
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTD4906N
PACKAGE DIMENSIONS
IPAK (STRAIGHT LEAD DPAK)
CASE 369D−01
NOTES:
ISSUE B
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
C
B
R
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
4
2
Z
A
K
1
3
2.29 BSC
−T−
SEATING
PLANE
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
0.155
−−−
F
H
STYLE 2:
PIN 1. GATE
2. DRAIN
D 3 PL
G
M
T
0.13 (0.005)
3. SOURCE
4. DRAIN
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD−01
ISSUE O
NOTES:
E
A
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
E3
E2
A1
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
L2
L1
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
D2
D
L
MILLIMETERS
DIM MIN
MAX
2.38
0.60
1.10
0.89
1.10
6.22
−−−
A
A1
A2
b
b1
D
D2
E
E2
E3
e
2.19
0.46
0.87
0.69
0.77
5.97
4.80
6.35
4.70
4.45
T
SEATING
PLANE
b1
A1
e
2X
A2
E2
6.73
−−−
5.46
3X b
M
0.13
T
2.28 BSC
D2
L
L1
L2
3.40
−−−
0.89
3.60
2.10
1.27
OPTIONAL
CONSTRUCTION
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
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Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NTD4906N/D
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