NTD5865 [ONSEMI]

N-Channel Power MOSFET;
NTD5865
型号: NTD5865
厂家: ONSEMI    ONSEMI
描述:

N-Channel Power MOSFET

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中文:  中文翻译
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NTD5865NL  
N-Channel Power MOSFET  
60 V, 46 A, 16 mW  
Features  
Low Gate Charge  
Fast Switching  
http://onsemi.com  
High Current Capability  
100% Avalanche Tested  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(on)  
These Devices are Pb−Free, Halogen Free and are RoHS Compliant  
16 mW @ 10 V  
19 mW @ 4.5 V  
60 V  
46 A  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Parameter  
Drain−to−Source Voltage  
Symbol  
Value  
60  
Unit  
V
D
V
DSS  
Gate−to−Source Voltage − Continuous  
V
20  
V
GS  
GS  
N−Channel  
Gate−to−Source Voltage  
V
30  
V
− Non−Repetitive (t < 10 ms)  
G
p
Continuous Drain  
Current (R  
T
= 25°C  
= 100°C  
= 25°C  
I
46  
33  
71  
A
C
D
)
q
JC  
S
Steady  
State  
T
C
4
Power Dissipation  
(R  
T
C
P
W
D
)
q
JC  
4
Pulsed Drain Current  
t = 10 ms  
p
I
203  
A
DM  
Operating Junction and Storage Temperature  
T , T  
55 to  
175  
°C  
J
stg  
1
2
1
2
3
3
Source Current (Body Diode)  
I
46  
36  
A
mJ  
A
S
DPAK  
IPAK  
Single Pulse Drain−to−Source  
Avalanche Energy  
(L =  
0.1 mH)  
E
CASE 369AA  
(Surface Mount)  
STYLE 2  
CASE 369D  
(Straight Lead)  
STYLE 2  
AS  
AS  
I
27  
Lead Temperature for Soldering Purposes  
(1/8from case for 10 s)  
T
260  
°C  
L
MARKING DIAGRAMS  
& PIN ASSIGNMENT  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
4
Drain  
4
THERMAL RESISTANCE MAXIMUM RATINGS  
Drain  
Parameter  
Symbol  
Value  
Unit  
Junction−to−Case (Drain)  
R
2.1  
49  
°C/W  
q
q
JC  
Junction−to−Ambient − Steady State (Note 1)  
R
JA  
2
1. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.  
2
Drain  
1
3
1
2
3
Gate Source  
Gate Drain Source  
A
Y
WW  
= Assembly Location*  
= Year  
= Work Week  
5865NL = Device Code  
= Pb−Free Package  
G
* The Assembly Location code (A) is front side  
optional. In cases where the Assembly Location is  
stamped in the package, the front side assembly  
code may be blank.  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 5 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
September, 2014 − Rev. 4  
NTD5865NL/D  
 
NTD5865NL  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain−to−Source Breakdown Voltage  
V
V
GS  
= 0 V, I = 250 mA  
60  
V
(BR)DSS  
D
Drain−to−Source Breakdown Voltage  
Temperature Coefficient  
V
/T  
J
55  
mV/°C  
(BR)DSS  
Zero Gate Voltage Drain Current  
I
T = 25°C  
1.0  
100  
100  
mA  
DSS  
J
V
V
= 0 V,  
= 60 V  
GS  
DS  
T = 150°C  
J
Gate−to−Source Leakage Current  
ON CHARACTERISTICS (Note 2)  
Gate Threshold Voltage  
I
V
= 0 V, V =  
GS  
20 V  
nA  
GSS  
DS  
V
V
= V , I = 250 mA  
1.0  
2.0  
V
GS(TH)  
GS  
DS  
D
Negative Threshold Temperature Co-  
efficient  
V
/T  
5.6  
mV/°C  
GS(TH)  
J
Drain−to−Source on Resistance  
Drain−to−Source on Resistance  
Forward Transconductance  
R
R
V
= 10 V, I = 20 A  
13  
16  
15  
16  
19  
mW  
mW  
S
DS(on)  
GS  
D
V
GS  
= 4.5 V, I = 20 A  
D
DS(on)  
gFS  
V
= 15 V, I = 20 A  
DS D  
CHARGES, CAPACITANCES AND GATE RESISTANCES  
Input Capacitance  
C
1400  
137  
95  
29  
1.1  
4
pF  
nC  
iss  
V
= 0 V, f = 1.0 MHz,  
GS  
Output Capacitance  
C
oss  
V
DS  
= 25 V  
Reverse Transfer Capacitance  
Total Gate Charge  
C
rss  
Q
Q
G(TOT)  
Threshold Gate Charge  
Gate−to−Source Charge  
Gate−to−Drain Charge  
Total Gate Charge  
Q
G(TH)  
V
GS  
= 10 V, V = 48 V,  
DS  
I
D
= 40 A  
Q
GS  
GD  
Q
8
V
GS  
= 4.5 V, V = 48 V,  
15  
nC  
G(TOT)  
DS  
I
D
= 40 A  
Gate Resistance  
R
1.3  
W
G
SWITCHING CHARACTERISTICS (Note 3)  
Turn−On Delay Time  
Rise Time  
t
8.4  
12.4  
26  
ns  
d(on)  
t
r
V
I
= 10 V, V = 48 V,  
DD  
GS  
= 40 A, R = 2.5 W  
D
G
Turn−Off Delay Time  
Fall Time  
t
d(off)  
t
f
4.4  
DRAIN−SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
T = 25°C  
0.95  
0.85  
20  
1.2  
V
SD  
J
V
= 0 V,  
= 40 A  
GS  
I
S
T = 125°C  
J
Reverse Recovery Time  
Charge Time  
t
ns  
RR  
ta  
13  
V
GS  
= 0 V, dIs/dt = 100 A/ms,  
I
S
= 40 A  
Discharge Time  
tb  
7
Reverse Recovery Charge  
Q
13  
nC  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
2. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.  
3. Switching characteristics are independent of operating junction temperatures.  
http://onsemi.com  
2
 
NTD5865NL  
TYPICAL CHARACTERISTICS  
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
4 V  
V
= 10 V  
V
DS  
10 V  
GS  
3.8 V  
70  
60  
50  
40  
30  
20  
10  
0
T = 25°C  
J
4.5 V  
3.6 V  
3.4 V  
3.2 V  
T = 25°C  
J
3 V  
2.8 V  
T = 125°C  
J
T = −55°C  
J
2.6 V  
3
0
1
2
4
5
1
2
3
4
5
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
Figure 1. On−Region Characteristics  
Figure 2. Transfer Characteristics  
0.030  
0.025  
0.020  
0.015  
0.010  
0.018  
0.016  
0.014  
0.012  
0.010  
T = 25°C  
J
I
= 40 A  
D
T = 25°C  
V
= 4.5 V  
= 10 V  
J
GS  
V
GS  
2
3
4
5
6
7
8
9
10  
5
10  
15  
20  
25  
30  
35  
40  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
I , DRAIN CURRENT (A)  
D
Figure 3. On−Resistance vs. Gate Voltage  
Figure 4. On−Resistance vs. Drain Current  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
10000  
1000  
100  
I
= 38 A  
= 10 V  
D
V
GS  
= 0 V  
V
GS  
T = 150°C  
J
T = 125°C  
J
−50 −25  
0
25  
50  
75  
100 125 150 175  
10  
20  
30  
40  
50  
60  
T , JUNCTION TEMPERATURE (°C)  
J
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 5. On−Resistance Variation with  
Temperature  
Figure 6. Drain−to−Source Leakage Current  
vs. Voltage  
http://onsemi.com  
3
NTD5865NL  
TYPICAL CHARACTERISTICS  
10  
1800  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
Q
V
= 0 V  
T
GS  
T = 25°C  
J
8
6
4
2
0
C
iss  
Q
gs  
Q
gd  
V
DS  
= 48 V  
I
D
= 40 A  
C
oss  
T = 25°C  
J
C
rss  
0
10  
20  
30  
40  
50  
60  
0
5
10  
15  
20  
25  
30  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Q , TOTAL GATE CHARGE (nC)  
g
Figure 7. Capacitance Variation  
Figure 8. Gate−to−Source vs. Total Charge  
1000  
100  
10  
40  
35  
30  
25  
20  
15  
10  
5
V
= 0 V  
GS  
V
I
= 48 V  
= 40 A  
= 10 V  
DD  
T = 25°C  
J
D
V
GS  
t
d(off)  
t
r
t
d(on)  
t
f
1
0
1
10  
R , GATE RESISTANCE (W)  
100  
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00  
V
SD  
, SOURCE−TO−DRAIN VOLTAGE (V)  
G
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
1000  
V
GS  
= 10 V  
SINGLE PULSE  
= 25°C  
T
C
100 ms  
100  
10  
1
10 ms  
1 ms  
10 ms  
dc  
R
LIMIT  
DS(on)  
THERMAL LIMIT  
PACKAGE LIMIT  
0.1  
0.1  
1
10  
100  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
http://onsemi.com  
4
NTD5865NL  
TYPICAL CHARACTERISTICS  
10  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.05  
0.02  
0.1  
0.01  
0.01  
SINGLE PULSE  
0.000001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
t, PULSE TIME (s)  
Figure 12. Thermal Response  
ORDERING INFORMATION  
Order Number  
Package  
Shipping  
NTD5865NL−1G  
IPAK (Straight Lead)  
(Pb−Free)  
75 Units / Rail  
NTD5865NLT4G  
DPAK  
(Pb−Free)  
2500 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
5
NTD5865NL  
PACKAGE DIMENSIONS  
DPAK (SINGLE GUAGE)  
CASE 369AA  
ISSUE B  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
2. CONTROLLING DIMENSION: INCHES.  
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-  
MENSIONS b3, L3 and Z.  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
FLASH, PROTRUSIONS, OR BURRS. MOLD  
FLASH, PROTRUSIONS, OR GATE BURRS SHALL  
NOT EXCEED 0.006 INCHES PER SIDE.  
5. DIMENSIONS D AND E ARE DETERMINED AT THE  
OUTERMOST EXTREMES OF THE PLASTIC BODY.  
6. DATUMS A AND B ARE DETERMINED AT DATUM  
PLANE H.  
C
A
D
A
E
c2  
b3  
B
4
2
L3  
L4  
Z
H
DETAIL A  
1
3
INCHES  
DIM MIN MAX  
0.086 0.094  
A1 0.000 0.005  
0.025 0.035  
MILLIMETERS  
MIN  
2.18  
0.00  
0.63  
0.76  
4.57  
0.46  
0.46  
5.97  
6.35  
MAX  
2.38  
0.13  
0.89  
1.14  
5.46  
0.61  
0.61  
6.22  
6.73  
A
b2  
c
b
b
b2 0.030 0.045  
b3 0.180 0.215  
M
0.005 (0.13)  
C
H
e
c
0.018 0.024  
c2 0.018 0.024  
GAUGE  
SEATING  
PLANE  
L2  
PLANE  
C
D
E
e
0.235 0.245  
0.250 0.265  
0.090 BSC  
2.29 BSC  
9.40 10.41  
1.40 1.78  
2.74 REF  
0.51 BSC  
0.89 1.27  
H
L
L1  
L2  
0.370 0.410  
0.055 0.070  
0.108 REF  
L
A1  
L1  
0.020 BSC  
DETAIL A  
ROTATED 905 CW  
L3 0.035 0.050  
L4  
Z
−−− 0.040  
0.155 −−−  
−−−  
3.93  
1.01  
−−−  
STYLE 2:  
PIN 1. GATE  
2. DRAIN  
SOLDERING FOOTPRINT*  
6.20  
0.244  
3.00  
0.118  
3. SOURCE  
4. DRAIN  
2.58  
0.102  
5.80  
0.228  
1.60  
0.063  
6.17  
0.243  
mm  
inches  
ǒ
Ǔ
SCALE 3:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
6
NTD5865NL  
PACKAGE DIMENSIONS  
IPAK  
CASE 369D  
ISSUE C  
C
B
R
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
V
S
E
INCHES  
DIM MIN MAX  
MILLIMETERS  
4
2
MIN  
5.97  
6.35  
2.19  
0.69  
0.46  
0.94  
MAX  
6.35  
6.73  
2.38  
0.88  
0.58  
1.14  
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245  
0.250 0.265  
0.086 0.094  
0.027 0.035  
0.018 0.023  
0.037 0.045  
0.090 BSC  
0.034 0.040  
0.018 0.023  
0.350 0.380  
0.180 0.215  
0.025 0.040  
0.035 0.050  
A
K
1
3
−T−  
SEATING  
PLANE  
2.29 BSC  
0.87  
0.46  
8.89  
4.45  
0.63  
0.89  
3.93  
1.01  
0.58  
9.65  
5.45  
1.01  
1.27  
−−−  
J
F
H
0.155  
−−−  
D 3 PL  
STYLE 2:  
PIN 1. GATE  
G
M
T
0.13 (0.005)  
2. DRAIN  
3. SOURCE  
4. DRAIN  
ON Semiconductor and the  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.  
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed  
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets  
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USA/Canada  
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For additional information, please contact your local  
Sales Representative  
NTD5865NL/D  

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