NTMFSC006N12MC [ONSEMI]
N-Channel Dual CoolTM 56 PowerTrench® MOSFET 120 V, 92 A, 6.0mΩ;型号: | NTMFSC006N12MC |
厂家: | ONSEMI |
描述: | N-Channel Dual CoolTM 56 PowerTrench® MOSFET 120 V, 92 A, 6.0mΩ |
文件: | 总7页 (文件大小:379K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET - Power, DUAL
COOL) N-Channel, DFN8
120 V, 6.1 mW, 92 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
120 V
6.1 mW @ 10 V
92 A
N−CHANNEL MOSFET
NTMFSC006N12MC
Features
• Advanced Dual−sided Cooled Packaging
• Ulra Low R
DS(on)
• MSL1 Robust Packaging Design
Typical Applications
• Primary DC−DC FET
• Synchronous Rectifier
• DC−DC Conversion
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
120
20
Unit
V
MARKING DIAGRAM
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain Cur- Steady
T
= 25°C
= 100°C
= 25°C
I
92
A
C
D
rent R
(Notes 1, 3)
State
q
JC
T
C
57
Power Dissipation
(Note 1)
T
C
P
104
41
W
A
D
D
R
q
JC
T
C
= 100°C
DFN8 5x6.15
CASE 506EG
Continuous Drain
Current R
Steady
State
T = 25°C
A
I
D
14
q
JA
T = 100°C
A
9
(Notes 1, 2, 3)
Power Dissipation
T = 25°C
A
P
2.7
1.1
1459
+150
86
W
MARKING DIAGRAM
R
(Notes 1, 2)
q
JA
T = 100°C
A
3RAYWZ
Pulsed Drain Current
T
C
= 25°C, t = 10 ms
I
DM
A
°C
A
p
Operating Junction / Storage Temperature Max
Source Current (Body Diode)
T , T
J stg
I
S
Single Pulse Drain−to−Source Avalanche
E
AS
114
mJ
Energy (I
= 53 A)
L(pk)
3R
A
Y
= Specific Device Code
= Assembly Location
= Year
Lead Temperature Soldering Reflow for Solder-
ing Purposes (1/8″ from case for 10 s)
T
L
260
°C
W
Z
= Work Week
= Assembly Lot Code
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
ORDERING INFORMATION
Parameter
Symbol
Value
1.2
Unit
†
Device
NTMFSC006N12MC
Package
Shipping
Junction−to−Case − Steady State
Junction−to−Case Top − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
DFN8
(Pb−Free)
3000 / Tape
& Reel
R
1.53
45
q
JT
R
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
2
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2023 − Rev. 3
NTMFSC006N12MC/D
NTMFSC006N12MC
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
120
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
I
D
= 250 mA, ref to 25°C
16
mV/°C
(BR)DSS
T
J
Zero Gate Voltage Drain Current
I
V
DS
= 0 V,
T = 25°C
5
mA
DSS
GS
J
V
= 120 V
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Gate−Resistance
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 250 mA
2
4
V
mV/°C
mW
W
GS(TH)
GS
DS
D
V
/T
J
I = 250 mA, ref to 25°C
D
9.8
4.7
1.4
GS(TH)
R
V
GS
= 10 V
I = 44 A
D
6.1
DS(on)
R
T = 25°C
A
G
CHARGES & CAPACITANCES
Input Capacitance
C
V
= 0 V, f = 1 MHz, V = 60 V
3040
1460
11.5
24.3
39
pF
nC
ISS
GS
DS
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
Total Gate Charge
C
Q
V
= 6 V, V = 60 V, I = 44 A
DS D
G(TOT)
G(TOT)
GS
Total Gate Charge
Q
V
GS
= 10 V, V = 60 V, I = 44 A
DS D
Gate−to−Source Charge
Gate−to−Drain Charge
Q
Q
13.2
6.3
GS
GD
GP
Plateau Voltage
V
4.65
V
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
V
= 10 V, V = 60 V,
15.2
5.3
ns
d(ON)
GS
D
DS
I
= 44 A, R = 2.5 W
G
Rise Time
t
r
Turn−Off Delay Time
t
25.5
5.7
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
V
S
= 0 V,
T = 25°C
0.86
0.74
V
GS
J
I
= 44 A
T = 125°C
J
Reverse Recovery Time
t
V
GS
= 0 V, dI /dt = 1000 A/ms,
33.4
ns
RR
S
I
= 44 A
S
Reverse Recovery Charge
Q
350.2
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTMFSC006N12MC
TYPICAL CHARACTERISTICS
120
100
90
V
GS
= 10 V to 5.8 V
V
DS
= 10 V
100
80
5.6 V
80
5.4 V
5.2 V
70
60
50
40
30
20
60
5.0 V
4.8 V
T = 25°C
J
40
20
0
10
0
T = 125°C
J
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
2
3
4
5
6
7
8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
6.0
5.8
5.6
5.4
5.2
5.0
20
18
16
14
12
10
8
T = 25°C
D
J
T = 25°C
J
I
= 44 A
V
= 10 V
GS
4.8
4.6
4.4
4.2
4.0
6
4
5
6
7
8
9
10
20
30
40
50
60
70
80
90 100
V
GS
, GATE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.2
1E+05
1E+04
1E+03
1E+02
1E+01
V
I
= 10 V
= 44 A
GS
T = 150°C
2.0
1.8
1.6
1.4
1.2
J
D
T = 125°C
J
T = 85°C
J
T = 25°C
J
1.0
0.8
0.6
1E+00
1E−01
0
20
40
60
80
100
120
−50
−25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Maximum Continuous Drain Current
vs. Case Temperature
Temperature
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3
NTMFSC006N12MC
TYPICAL CHARACTERISTICS
10,000
1000
100
10
C
ISS
9
8
7
6
5
4
3
2
C
OSS
Q
Q
GD
GS
10
1
V
I
= 60 V
= 44 A
V
= 0 V
DS
GS
C
RSS
T = 25°C
D
J
1
0
T = 25°C
J
f = 1 MHz
0
1
1
20
40
60
80
100
120
0
5
10
15
20
25
30
35
40
V
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
DS
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
1000
100
V
V
= 10 V
= 60 V
= 44 A
V
= 0 V
GS
GS
DS
I
D
10
1
t
d(off)
t
d(on)
10
1
T = 125°C
J
t
f
t
r
T = 25°C
J
T = −55°C
J
0.1
10
R , GATE RESISTANCE (W)
100
0.3 0.4
V
0.5
0.6
0.7
0.8
0.9
1.0 1.1
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
100
10
10 ms
T
= 25°C
J(initial)
100 ms
T
= 100°C
J(initial)
10
V
≤ 10 V
Single Pulse
= 25°C
GS
T
C
1 ms
1
R
Limit
DS(on)
10 ms
Thermal Limit
Package Limit
100 ms
0.1
1
10
100
1E−06 1E−05
1E−04
1E−03
1E−02 1E−01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (sec)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NTMFSC006N12MC
TYPICAL CHARACTERISTICS
10
50% Duty Cycle
1
0.1
20%
10%
5%
2%
0.01
1%
0.001
Single Pulse
0.0001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DUAL COOL is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6.15, 1.27P, DUAL COOL
CASE 506EG
ISSUE D
DATE 25 AUG 2020
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXX
XXXX = Specific Device Code
*This information is generic. Please refer to
A
Y
= Assembly Location
= Year
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84257G
DFN8 5x6.15, 1.27P, DUAL COOL
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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