NTQD6866R2G [ONSEMI]
Power MOSFET 6.9 Amps, 20 Volts N-Channel TSSOP-8;
| 型号： | NTQD6866R2G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 6.9 Amps, 20 Volts N-Channel TSSOP-8 局域网 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTQD6866R2
Power MOSFET
6.9 Amps, 20 Volts
N−Channel TSSOP−8
Features
• New Low Profile TSSOP−8 Package
• Ultra Low R
http://onsemi.com
DS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
6.9 AMPERES
20 VOLTS
30 mW @ VGS = 4.5 V
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• I
and V
Specified at Elevated Temperatures
DSS
DS(on)
• Pb−Free Package is Available
N−Channel
N−Channel
Applications
D
D
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Phones
• Battery Applications
• NoteBook PC
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
G1
G2
Rating
Drain−to−Source Voltage
Symbol Value
Unit
Vdc
Vdc
Vdc
V
DSS
DGR
20
20
S1
S2
Drain−to−Gate Voltage (R = 1.0 MW)
V
GS
Gate−to−Source Voltage − Continuous
V
GS
"12
Thermal Resistance − Single Die
Junction−to−Ambient (Note 1)
MARKING DIAGRAM &
PIN ASSIGNMENT
R
62.5
2.0
6.9
24
°C/W
W
Adc
Adc
q
P
D
D
JA
Total Power Dissipation @ T = 25°C
A
D D D
D
Continuous Drain Current @ T = 25°C
I
A
8
Pulsed Drain Current (Note 4)
I
DM
Thermal Resistance − Single Die
Junction−to−Ambient (Note 2)
1
R
88
1.42
5.8
4.6
20
°C/W
W
Adc
Adc
Adc
866
YWW
A G
q
JA
Total Power Dissipation @ T = 25°C
P
I
I
A
D
D
D
Continuous Drain Current @ T = 25°C
TSSOP−8
CASE 948S
PLASTIC
A
Continuous Drain Current @ T = 70°C
A
Pulsed Drain Current (Note 4)
I
DM
1
Thermal Resistance − Single Die
Junction−to−Ambient (Note 3)
S1
G1 S2 G2
R
132
0.94
4.7
3.8
14
°C/W
W
Adc
Adc
Adc
q
P
JA
D
D
D
Total Power Dissipation @ T = 25°C
A
Continuous Drain Current @ T = 25°C
I
I
A
866
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
Continuous Drain Current @ T = 70°C
A
Pulsed Drain Current (Note 4)
I
DM
Operating and Storage Temperature Range
T , T
J
−55 to
+150
°C
stg
= Work Week
= Pb−Free Package
Single Pulse Drain−to−Source Avalanche
E
mJ
AS
Energy − Starting T = 25°C
150
260
ORDERING INFORMATION
J
(V = 20 Vdc, V = 5.0 Vdc,
DD
GS
†
Peak I = 5.5 Apk, L = 10 mH, R = 25 W)
Device
Package
Shipping
L
G
Maximum Lead Temperature for Soldering
Purposes for 10 seconds
T
°C
L
NTQD6866R2
TSSOP−8 4000/Tape & Reel
NTQD6866R2G
TSSOP−8 4000/Tape & Reel
(Pb−Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
RecommendedOperating Conditions may affect device reliability.
1. Mounted onto a 2″ square FR−4 board
†For information on tape and reel specifications,
includingpart orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
(1 in sq, 2 oz Cu 0.06″ thick single−sided), t < 10 seconds.
2. Mounted onto a 2″ square FR−4 board
(1 in sq, 2 oz Cu 0.06″ thick single−sided), t = ss.
3. Minimum FR−4 or G−10 PCB, t = steady state.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 3
NTQD6866R2/D
NTQD6866R2
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 250 mAdc)
20
−
−
−
GS
D
Temperature Coefficient (Positive)
−
18.5
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
DSS
(V = 0 Vdc, V = 20 Vdc, T = 25°C)
−
−
−
−
1.0
10
GS
DS
J
(V = 0 Vdc, V = 20 Vdc, T = 100°C)
GS
DS
J
Gate−Body Leakage Current
(V 12 Vdc, V = 0 Vdc)
I
nAdc
Vdc
GSS
=
−
−
100
GS
DS
ON CHARACTERISTICS
Gate Threshold Voltage
V
R
GS(th)
(V = V , I = 250 mAdc)
0.6
−
0.9
−2.7
1.2
−
DS
GS D
Temperature Coefficient (Negative)
mV/°C
Static Drain−to−Source On−State Resistance
W
DS(on)
(V = 4.5 Vdc, I = 6.9 Adc)
−
−
−
−
0.026
0.025
0.030
0.030
0.032
0.030
0.038
0.038
GS
D
(V = 4.5 Vdc, I = 5.8 Adc)
GS
D
(V = 2.5 Vdc, I = 3.5 Adc)
GS
D
(V = 2.5 Vdc, I = 2.9 Adc)
GS
D
Forward Transconductance
(V = 10 Vdc, I = 5.8 Adc)
g
Mhos
pF
FS
−
14
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
875
325
100
1400
550
iss
(V = 16 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
C
oss
f = 1.0 MHz)
C
175
rss
t
−
−
−
−
−
−
−
−
−
−
−
10
45
40
90
8.0
45
35
75
13
1.8
4.5
18
80
75
150
−
ns
d(on)
t
r
(V = 16 Vdc, I = 5.8 Adc,
DD
GS
D
V
= 4.5 Vdc, R = 6.0 W)
G
Turn−Off Delay Time
Fall Time
t
t
t
d(off)
t
f
Turn−On Delay Time
Rise Time
d(on)
t
−
r
(V = 16 Vdc, I = 5.8 Adc,
DD
GS
D
V
= 4.5 Vdc, R = 3.0 W)
G
Turn−Off Delay Time
Fall Time
−
d(off)
t
−
f
Gate Charge
Q
22
−
nC
tot
gs
gd
(V = 16 Vdc, V = 4.5 Vdc,
DS
GS
= 5.8 Adc)
Q
Q
I
D
−
BODY−DRAIN DIODE RATINGS
Forward On−Voltage
(I = 5.8 Adc, V = 0 Vdc)
V
−
−
0.85
0.75
1.0
Vdc
ns
S
GS
SD
(I = 5.8 Adc, V = 0 Vdc, T = 100°C)
−
S
GS
J
Reverse Recovery Time
t
−
−
−
−
23
11
−
−
−
−
rr
(I = 5.8 Adc, V = 0 Vdc,
S
GS
t
V
S
= 20 Vdc
b
DS
dI /dt = 100 A/ms)
t
12
a
Reverse Recovery Stored Charge
Q
0.013
mC
RR
5. Switching characteristics are independent of operating junction temperature.
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2
NTQD6866R2
16
18
16
2 V
V
DS
≥ 10 V
5 V
14
12
10
8
V
GS
= 10 V
T = 25°C
J
14
12
10
8
1.8 V
1.6 V
3 V
2.2 V
6
6
T = 25°C
J
4
2
0
4
1.4 V
1.2 V
T = 100°C
2
J
T = −55°C
J
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0.5
1
1.5
2
2.5
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.045
0.04
0.04
0.03
0.02
0.01
T = 25°C
J
I
= 5.8 A
D
T = 25°C
J
0.035
0.03
V
= 2.5 V
= 4.5 V
GS
0.025
0.02
V
GS
0.015
0.01
0
2
4
6
8
0
4
6
8
10
12
14
16
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
1000
2
V
GS
= 0 V
I
V
= 2.9 A
D
= 4.5 V
GS
T = 150°C
J
1.5
1
100
10
T = 100°C
J
0.5
−50 −25
0
25
50
75
100
125
150
0
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
versus Voltage
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3
NTQD6866R2
5
2500
2000
V
V
= 0 V
= 0 V
T = 25°C
DS
GS
J
Q
T
C
C
iss
4
3
2
1
V
GS
rss
1500
1000
500
0
Q
Q
2
1
C
iss
C
oss
I
D
= 5.8 A
C
T = 25°C
J
rss
0
0
V
GS
V
DS
10
5
0
5
10
15
20
2
4
6
8
10
12
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage
versus Total Charge
1000
10
8
V
I
= 16 V
= 5.8 A
= 4.5 V
V
= 0 V
DD
GS
T = 25°C
J
D
V
GS
100
10
1
t
f
6
t
r
t
d(off)
4
t
d(on)
2
0
1
10
R , GATE RESISTANCE (W)
100
0.4
0.5
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
0.6
0.7
0.8
V
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
100
V
GS
= 20 V
T = 25°C
C
SINGLE PULSE
100 ms
1 ms
10
1
di/dt
I
S
10 ms
t
rr
t
t
a
b
R
Limit
TIME
DS(on)
0.1
Thermal Limit
Package Limit
dc
0.25 I
t
S
p
I
S
0.01
0.1
1
10
100
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Diode Reverse Recovery Waveform
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4
NTQD6866R2
10
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.001
Single Pulse
0.0001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t, TIME (s)
Figure 13. Thermal Response
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE C
DATE 20 JUN 2008
SCALE 2:1
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
S
0.20 (0.008) T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
U
0.20 (0.008) T
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
0.114
DIM MIN
MAX
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
3.10
−W−
4.50 0.169
1.10 ---
C
C
0.076 (0.003)
D
0.05
0.50
0.15 0.002
0.70 0.020
F
DETAIL E
SEATING
PLANE
D
−T−
G
G
J
0.65 BSC
0.026 BSC
0.09
0.09
0.19
0.19
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
GENERIC
MARKING DIAGRAM*
F
XXX
YWW
A G
DETAIL E
G
XXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW = Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
98AON00697D
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: TSSOP−8
PAGE 1 OF2
DOCUMENT NUMBER:
98AON00697D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
A
B
RELEASED FOR PRODUCTION.
18 APR 2000
13 JAN 2006
13 MAR 2006
ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS.
CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C.
REBELLO.
C
REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED
MARKING INFORMATION. REQ. BY C. REBELLO.
20 JUN 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
June, 2008 − Rev. 01C
948S
onsemi,
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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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相关型号：
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NTQD6968NR2
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