NTTFS4H05NTAG [ONSEMI]
Power MOSFET Single NâChannel;
| 型号： | NTTFS4H05NTAG |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET Single NâChannel 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTTFS4H05N
Power MOSFET
25 V, 94 A, Single N−Channel, m8−FL
Features
• Optimized Design to Minimize Conduction and Switching Losses
• Optimized Package to Minimize Parasitic Inductances
• Optimized material for improved thermal performance
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• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
V
GS
MAX R
TYP Q
GTOT
DS(on)
• High Performance DC-DC Converters
• System Voltage Rails
• Netcom, Telecom
4.5 V
10 V
4.8 mW
8.7 nC
18.9 nC
3.3 mW
• Servers & Point of Load
PIN CONNECTIONS
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
m8−FL (3.3 x 3.3 mm)
Parameter
Drain-to-Source Voltage
Symbol
Value
25
Units
V
DSS
V
V
A
Gate-to-Source Voltage
V
GS
20
Continuous Drain Current R
(T = 25°C, Note 1)
A
I
D
22.4
q
JA
JC
(Top View)
(Bottom View)
Power Dissipation R
P
D
2.66
94
W
A
q
JA
(T = 25°C, Note 1)
A
Continuous Drain Current R
I
D
q
(T = 25°C, Note 1)
C
N−CHANNEL MOSFET
Power Dissipation R
(T = 25°C, Note 1)
C
P
D
46.3
W
q
JC
D (5−8)
Pulsed Drain Current (t = 10 ms)
I
304
84
A
p
DM
Single Pulse Drain-to-Source Avalanche
Energy (Note 1)
E
mJ
AS
G (4)
(I = 41 A , L = 0.1 mH) (Note 3)
L
pk
Drain to Source dV/dt
dV/dt
7
V/ns
°C
S (1,2,3)
Maximum Junction Temperature
Storage Temperature Range
T
150
J(max)
T
STG
−55 to
150
°C
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Lead Temperature Soldering Reflow (SMD
Styles Only), Pb-Free Versions (Note 2)
T
SLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
2
1. Values based on copper area of 645 mm (or 1 in ) of 2 oz copper thickness
and FR4 PCB substrate.
2. For more information, please refer to our Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
3. This is the absolute maximum rating. Parts are 100% UIS tested at T = 25°C,
J
V
GS
= 10 V, I = 27 A, E = 36 mJ.
L AS
THERMALCHARACTERISTICS
Parameter
Symbol
Max
Units
Thermal Resistance,
Junction-to-Ambient (Note 1 and 4)
Junction-to-Case (Note 1 and 4)
°C/W
R
47
2.7
q
JA
JC
R
q
4. Thermal Resistance R
and R
as defined in JESD51−3.
JC
q
q
JA
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
July, 2015 − Rev. 3
NTTFS4H05N/D
NTTFS4H05N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
25
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
15
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
V
= 0 V,
= 20 V
T = 25°C
1.0
20
DSS
GS
DS
J
mA
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
100
nA
GSS
DS
GS
V
V
GS
= V , I = 250 mA
1.2
2.1
V
GS(TH)
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
3.8
2.5
3.8
69
mV/°C
GS(TH)
J
R
V
= 10 V
I
I
= 30 A
= 30 A
3.3
4.8
DS(on)
GS
D
mW
V
GS
= 4.5 V
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
V
= 12 V, I = 15 A
S
DS
D
C
1205
835
45
ISS
Output Capacitance
C
C
V
= 0 V, f = 1 MHz, V = 12 V
pF
nC
OSS
RSS
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
8.7
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
2.7
G(TH)
V
= 4.5 V, V = 12 V; I = 30 A
DS D
GS
Q
3.6
GS
Q
1.88
18.9
1.0
GD
Q
V
= 10 V, V = 12 V; I = 30 A
nC
G(TOT)
GS
DS
D
Gate Resistance
R
T = 25°C
A
2
W
G
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
t
8.9
32
d(ON)
Rise Time
t
r
V
GS
= 4.5 V, V = 12 V, I = 15 A,
DS D
ns
R
= 3.0 W
G
Turn−Off Delay Time
t
14.6
3
d(OFF)
Fall Time
t
f
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
t
6.0
27
d(ON)
Rise Time
t
r
V
GS
= 10 V, V = 12 V,
DS
ns
V
I
= 15 A, R = 3.0 W
D
G
Turn−Off Delay Time
t
18.6
2.3
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T = 25°C
J
0.78
0.6
1.1
V
I
= 0 V,
GS
S
= 10 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
30.8
15
RR
t
t
ns
a
V
GS
= 0 V, dIS/dt = 100 A/ms,
I
S
= 10 A
Discharge Time
15.8
20
b
nC
Reverse Recovery Charge
Q
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NTTFS4H05N
TYPICAL CHARACTERISTICS
4.2 V
4.0 V
V
= 3.6 V
= 3.4 V
= 3.2 V
140
120
100
80
140
120
100
80
GS
GS
GS
3.8 V
V
DS
= 5 V
4.5 V
10 V
V
V
V
T = 25°C
J
= 3.0 V
= 2.8 V
GS
T = 125°C
J
60
60
V
GS
40
40
T = 25°C
J
V
V
= 2.6 V
= 2.4 V
GS
20
0
20
0
GS
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.0050
0.0046
0.0042
0.0038
0.0034
0.0030
0.0050
0.0046
0.0042
0.0038
0.0034
0.0030
0.0026
0.0022
0.0018
T = 25°C
I
D
= 30 A
V
= 4.5 V
GS
V
= 10 V
0.0026
0.0022
GS
0.0014
0.0010
3
4
5
6
7
8
9
10
20 30 40 50 60
70 80 90 100 110 120
V
GS
(V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
1E−04
1E−05
1E−06
1E−07
1E−08
V
GS
= 0 V
I
V
= 30 A
T = 150°C
D
J
= 10 V
GS
T = 125°C
J
T = 85°C
J
1E−09
1E−10
T = 25°C
J
0.8
0.7
−50 −25
0
25
50
75
100
125
150
5
10
15
20
25
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTTFS4H05N
TYPICAL CHARACTERISTICS
2200
2000
1800
1600
1400
1200
1000
800
10
Q
T
T = 25°C
GS
J
V
= 0 V
8
6
4
C
C
iss
Q
Q
gd
gs
oss
T = 25°C
J
600
V
V
I
= 10 V
GS
2
0
400
= 12.0 V
DD
= 30 A
200
0
D
C
rss
0
5
10
15
20
25
0
2
4
6
8
10 12 14 16 18 20
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
30
25
20
15
10
1000
100
V
= 12 V
= 15 A
= 10 V
DD
V
GS
= 0 V
I
D
V
GS
t
d(off)
t
f
T = 125°C
J
T = 25°C
J
t
r
t
d(on)
10
1
5
0
1
10
R , GATE RESISTANCE (W)
100
0.4
0.5
0.6
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
40
35
30
25
20
15
10
1000
100
10
10 ms
I
D
= 27 A
100 ms
1 ms
10 ms
dc
1
0 V < V < 10 V
GS
R
Limit
0.1
DS(on)
Thermal Limit
Package Limit
5
0
0.01
0.01
0.1
1
10
100
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
NTTFS4H05N
TYPICAL CHARACTERISTICS
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
1
2
PCB Cu Area 650 mm
PCB Cu thk 1 oz
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
140
120
1E+03
100
80
1E+02
60
1E+01
1E+00
40
20
0
0
20
40
60
80
(A)
100
120
140
1E−07
1E−06
1E−05
1E−04
1E−03
I
D
PULSE WIDTH (sec)
Figure 14. GFS vs. ID
Figure 15. Avalanche Characteristics
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5
NTTFS4H05N
ORDERING INFORMATION
Device
†
Package
Shipping
NTTFS4H05NTAG
WDFN8
(Pb-Free)
1500 / Tape & Reel
5000 / Tape & Reel
NTTFS4H05NTWG
WDFN8
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAM
1
1
S
S
S
G
D
D
D
D
H05N
AYWWG
G
WDFN8
(m8FL)
CASE 511AB
H05N = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
−
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6
NTTFS4H05N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.028
0.000
0.009
0.006
0.80
0.05
0.40
0.25
4X
q
E1
c
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
SEATING
PLANE
0.13
1.50
−−−
0.005
0.059
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X
b
0.10
0.05
C
C
A B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
PITCH
4X
L
4X
0.66
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
BOTTOM VIEW
G
2.30
0.57
0.47
0.75
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NTTFS4H05N/D
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