NV24C08UVLT2G [ONSEMI]

EEPROM 串行 8-Kb I2C - 汽车级;


型号：	NV24C08UVLT2G
厂家：	ONSEMI
描述：	EEPROM 串行 8-Kb I2C - 汽车级可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总15页 (文件大小：485K)
中文：	中文翻译
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DATA SHEET

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EEPROM, Serial, 8-Kb I²C,

Low Voltage Automotive

Grade 1

US8

U SUFFIX

CASE 493

TSSOP−8

DT SUFFIX

CASE 948AL

NV24C08LV

Description

The NV24C08LV are 8−Kb CMOS Serial EEPROM devices that

operate at a minimum 1.7 V supply voltage. They are organized

internally as 64 pages of 16 bytes each. All devices support the

TSOP−5

SN SUFFIX

CASE 483

Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C

protocol.

Data is written by providing a starting address, then loading 1 to 16

contiguous bytes into a Page Write Buffer, and then writing all data to

non−volatile memory in one internal write cycle. Data is read by

providing a starting address and then shifting out data serially while

automatically incrementing the internal address count.

External address pins make it possible to address up to two

NV24C08 device on the same bus.

UDFN−8

MUW3 SUFFIX

CASE 517DH

SOIC8

DW SUFFIX

CASE 751BD

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the

package dimensions section on page 9 of this data sheet.

Features

• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified

• Supports Standard, Fast and Fast−Plus I C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 16−Byte Page Write Buffer

• Fast Write Time (4 ms max)

• Hardware Write Protection for Entire Memory

• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs

(SCL and SDA)

• Low power CMOS Technology

• More than 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Automotive Grade 1 Temperature Range

• SOIC, TSSOP, US 8−Lead, TSOP−5 Lead and Wettable Flank UDFN

8−pad Packages

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

PIN CONFIGURATION (SOIC−8,US−8,UNFN−8 ,TSSOP−8)

PIN CONFIGURATION (TSOP−5)

NV24C08

SCL

SDA

Publication Order Number:

NV24C08LV/D

October, 2021 − Rev. 2

NV24C08LV

Table 1. PIN FUNCTION

Pin Name

Function

Device Address Input

SCL

SDA

Serial Data Input/Output

Serial Clock Input

Write Protect Input

Power Supply

SCL

NV24C08LV

SDA

Ground

No Connect

Figure 1. Functional Symbol

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

Units

°C

Storage Temperature

−65 to +150

−0.5 to +6.5

Voltage on any pin with respect to Ground (Note 1)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A and WP

should not exceed V + 1 V for more than 20 ns, while voltage on the I C bus pins, SCL and SDA, should not exceed the absolute maximum

ratings, irrespective of V

Table 3. RELIABILITY CHARACTERISTICS

Symbol

(Note 2)

Parameter

Min

1,000,000

100

Units

Write Cycles (Note 3)

Years

Endurance

END

(Note 2)

Data Retention

2. T = 25°C

3. A Write Cycle refers to writing a Byte or a Page.

Table 4. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +125°C, unless otherwise speciﬁed.*)

Symbol

Parameter

Read Current

Test Conditions

= 1 MHz

SCL

Min

Max

0.3

0.5

Units

Read, f

Write

CCR

Write Current

CCW

Standby Current

All I/O Pins at GND or V

T = −40°C to +85°C

T = −40°C to +125°C

I/O Pin Leakage

Pin at GND or V

Input Low Voltage

Input High Voltage

Output Low Voltage

2.2 V ≤ V ≤ 5.5 V

−0.5

0.3 V

0.2 V

IL1

IL2

IH1

IH2

OL1

OL2

1.7 V ≤ V < 2.2 V

2.2 V ≤ V ≤ 5.5 V

0.7 V

0.8 V

+ 0.5

1.7 V ≤ V < 2.2 V

≥ 2.2 V, I = 6.0 mA

0.4

0.2

< 2.2 V, I = 2.0 mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

CC(min)

= 1.6 V for Read operations, T = −20°C to +85°C.

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NV24C08LV

Table 5. PIN IMPEDANCE CHARACTERISTICS V = 1.7 V to 5.5 V, T = −40°C to +125°C, unless otherwise speciﬁed.*)

Symbol

Parameter

Conditions

Max

Units

(Note 4)

SDA I/O Pin Capacitance

Input Capacitance (other pins)

= 0 V

, I

WP Input Current, Address Input

Current (A2)

< V , V = 5.5 V

(Note 5)

< V , V = 3.3 V

< V , V = 1.7 V

> V

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When not driven, the WP and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;

therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the

input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.

= 1.6 V for Read operations, T = −20°C to +85°C.

CC(min)

Table 6. A.C. CHARACTERISTICS V = 1.7 V to 5.5 V, T = −40°C to +125°C, unless otherwise speciﬁed.*) (Note 6)

Standard

Fast

Fast−Plus

Min

Max

Min

Max

Min

Max

Symbol

Parameter

Clock Frequency

Units

kHz

SCL

100

400

1,000

START Condition Hold Time

Low Period of SCL Clock

High Period of SCL Clock

START Condition Setup Time

Data In Hold Time

4.7

0.6

1.3

0.6

0.26

0.50

0.26

HD:STA

LOW

HIGH

4.7

SU:STA

HD:DAT

Data In Setup Time

250

100

SU:DAT

(Note 7)

SDA and SCL Rise Time

SDA and SCL Fall Time

STOP Condition Setup Time

1,000

300

120

t (Note 7)

0.6

1.3

0.26

0.5

SU:STO

Bus Free Time Between

STOP and START

4.7

BUF

SCL Low to Data Out Valid

Data Out Hold Time

3.5

0.9

0.45

(Note 7)

100

T (Note 7)

Noise Pulse Filtered at SCL

and SDA Inputs

WP Setup Time

WP Hold Time

Write Cycle Time

SU:WP

2.5

HD:WP

(Notes 7, 8) Power-up to Ready Mode

0.35

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

8. t is the delay between the time V is stable and the device is ready to accept commands.

CC(min)

= 1.6 V for Read operations, T = −20°C to +85°C.

Table 7. A.C. TEST CONDITIONS

Input Levels

0.2 x V to 0.8 x V for V ≥ 2.2 V

CC CC CC

0.15 x V to 0.85 x V for V < 2.2 V

Input Rise and Fall Times

Input Reference Levels

Output Reference Levels

Output Load

≤ 50 ns

0.3 x V , 0.7 x V

Current Source: I = 6 mA (V ≥ 2.2 V); I = 2 mA (V < 2.2 V); C = 100 pF

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NV24C08LV

Power−On Reset (POR)

During data transfer, the SDA line must remain stable

while the SCL line is high. An SDA transition while SCL is

high will be interpreted as a START or STOP condition

(Figure 2). The START condition precedes all commands. It

consists of a HIGH to LOW transition on SDA while SCL

is HIGH. The START acts as a ‘wake−up’ call to all

receivers. Absent a START, a Slave will not respond to

commands. The STOP condition completes all commands.

It consists of a LOW to HIGH transition on SDA while SCL

is HIGH.

Each NV24C08LV incorporates Power−On Reset (POR)

circuitry which protects the internal logic against powering

up in the wrong state.

A NV24C08LV device will power up into Standby mode

after V exceeds the POR trigger level and will power

down into Reset mode when V drops below the POR

trigger level. This bi−directional POR feature protects the

device against ‘brown−out’ failure following a temporary

loss of power.

NOTE: The I/O pins of NV24C08LV do not obstruct the SCL

and SDA lines if the VCC supply is switched off. During

power−up, the SCL and SDA pins (connected with pull−up

resistors to VCC) will follow the VCC monotonically from

VSS (0 V) to nominal VCC value, regardless of pull−up

resistor value. The delta between the VCC and the

instantaneous voltage levels during power ramping will be

determined by the relation between bus time constant

(determined by pull−up resistance and bus capacitance) and

actual VCC ramp rate.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master.

SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode, this pin

is open drain. Data is acquired on the positive edge, and is

delivered on the negative edge of SCL.

A2: The Address inputs set the device address when

cascading multiple devices. When not driven, this pin is

pulled LOW internally.

Device Addressing

WP: The Write Protect input pin inhibits all write

operations, when pulled HIGH. When not driven, this pin is

pulled LOW internally.

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. For normal Read/Write operations, the

first 4 bits of the Slave address are fixed at 1010 (Ah). The

next 3 bits are used as programmable address bits when

cascading multiple devices and/or as internal address bits.

The last bit of the slave address, R/W, specifies whether a

Read (1) or Write (0) operation is to be performed. The 3

address space extension bits are assigned as illustrated in

Functional Description

The NV24C08LV supports the Inter−Integrated Circuit

(I C) Bus data transmission protocol, which defines a device

that sends data to the bus as a transmitter and a device

receiving data as a receiver. Data flow is controlled by a

Master device, which generates the serial clock and all

START and STOP conditions. The NV24C08LV acts as a

Slave device. Master and Slave alternate as either

transmitter or receiver.

Figure 3. A must match the state of the external address pin,

and a and a are internal address bits.

Acknowledge

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA line

during the 9th clock cycle (Figure 4). The Slave will also

acknowledge the address byte and every data byte presented

in Write mode. In Read mode the Slave shifts out a data byte,

I²C Bus Protocol

The I C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the V supply via pull−up

resistors. Master and Slave devices connect to the 2−wire

bus via their respective SCL and SDA pins. The transmitting

device pulls down the SDA line to ‘transmit’ a ‘0’ and

releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see AC Characteristics).

and then releases the SDA line during the 9 clock cycle. As

long as the Master acknowledges the data, the Slave will

continue transmitting. The Master terminates the session by

not acknowledging the last data byte (NoACK) and by

issuing a STOP condition. Bus timing is illustrated in

Figure 5.

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NV24C08LV

SCL

SDA

START

CONDITION

STOP

CONDITION

Figure 2. Start/Stop Timing

R/W

N24C08

Figure 3. Slave Address Bits

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY

(RECEIVER)

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (w t

)

SU:DAT

ACK DELAY (v t

)

START

Figure 4. Acknowledge Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

SU:STO

SU:DAT

HD:STA

SDA IN

BUF

SDA OUT

Figure 5. Bus Timing

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NV24C08LV

WRITE OPERATIONS

Byte Write

sixteen bytes are received and the STOP condition has been

sent by the Master, the internal Write cycle begins. At this

point all received data is written to the NV24C08LV in a

single write cycle.

In Byte Write mode, the Master sends the START

condition and the Slave address with the R/W bit set to zero

to the Slave. After the Slave generates an acknowledge, the

Master sends the byte address that is to be written into the

address pointer of the NV24C08LV. After receiving another

acknowledge from the Slave, the Master transmits the data

byte to be written into the addressed memory location. The

NV24C08LV device will acknowledge the data byte and the

Master generates the STOP condition, at which time the

device begins its internal Write cycle to nonvolatile memory

Acknowledge Polling

The acknowledge (ACK) polling routine can be used to

take advantage of the typical write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation, the NV24C08LV initiates the internal write cycle.

The ACK polling can be initiated immediately. This

involves issuing the start condition followed by the slave

address for a write operation. If the NV24C08LV is still busy

with the write operation, NoACK will be returned. If the

NV24C08LV has completed the internal write operation, an

ACK will be returned and the host can then proceed with the

next read or write operation.

(Figure 6). While this internal cycle is in progress (t ), the

SDA output will be tri−stated and the NV24C08LV will not

respond to any request from the Master device (Figure 7).

Page Write

The NV24C08LV writes up to 16 bytes of data in a single

write cycle, using the Page Write operation (Figure 8). The

Page Write operation is initiated in the same manner as the

Byte Write operation, however instead of terminating after

the data byte is transmitted, the Master is allowed to send up

to fifteen additional bytes. After each byte has been

transmitted the NV24C08LV will respond with an

acknowledge and internally increments the four low order

address bits. The high order bits that define the page address

remain unchanged. If the Master transmits more than sixteen

bytes prior to sending the STOP condition, the address

counter ‘wraps around’ to the beginning of page and

previously transmitted data will be overwritten. Once all

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the operation of

the NV24C08LV. The state of the WP pin is strobed on the

last falling edge of SCL immediately preceding the first data

byte (Figure 9). If the WP pin is HIGH during the strobe

interval, the NV24C08LV will not acknowledge the data

byte and the Write request will be rejected.

Delivery State

The NV24C08LV is shipped erased, i.e., all bytes are FFh.

BUS ACTIVITY:

MASTER

ADDRESS

BYTE

DATA

BYTE

SLAVE

ADDRESS

− a

d − d

7 0

SLAVE

Figure 6. Byte Write Sequence

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NV24C08LV

SCL

SDA

Bit

ACK

Byte n

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 7. Write Cycle Timing

BUS ACTIVITY:

MASTER

DATA

ADDRESS

BYTE

SLAVE

ADDRESS

BYTE

n+1

BYTE

n+P

BYTE

SLAVE

n = 1

P v 15

Figure 8. Page Write Sequence

ADDRESS

BYTE

DATA

BYTE

SCL

SDA

SU:WP

HD:WP

Figure 9. WP Timing

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NV24C08LV

READ OPERATIONS

Immediate Read

address of the location it wishes to read. After the

NV24C08LV acknowledges the byte address, the Master

device resends the START condition and the slave address,

this time with the R/W bit set to one. The NV24C08LV then

responds with its acknowledge and sends the requested data

byte. The Master device does not acknowledge the data

(NoACK) but will generate a STOP condition (Figure 11).

Upon receiving a Slave address with the R/W bit set to ‘1’,

the NV24C08LV will interpret this as a request for data

residing at the current byte address in memory. The

NV24C08LV will acknowledge the Slave address, will

immediately shift out the data residing at the current address,

and will then wait for the Master to respond. If the Master

does not acknowledge the data (NoACK) and then follows

up with a STOP condition (Figure 10), the NV24C08LV

returns to Standby mode.

Sequential Read

If during a Read session, the Master acknowledges the 1

data byte, then the NV24C08LV will continue transmitting

data residing at subsequent locations until the Master

responds with a NoACK, followed by a STOP (Figure 12).

In contrast to Page Write, during Sequential Read the

address count will automatically increment to and then

wrap−around at end of memory (rather than end of page).

Selective Read

Selective Read operations allow the Master device to

select at random any memory location for a read operation.

The Master device first performs a ‘dummy’ write operation

by sending the START condition, slave address and byte

BUS ACTIVITY:

MASTER

A T

C O

K P

SLAVE

ADDRESS

DATA

SLAVE

BYTE

SCL

SDA

Bit

DATA OUT

NO ACK

STOP

Figure 10. Immediate Read Sequence and Timing

BUS ACTIVITY:

MASTER

A T

C O

K P

ADDRESS

BYTE

SLAVE

ADDRESS

SLAVE

ADDRESS

DATA

BYTE

SLAVE

Figure 11. Selective Read Sequence

BUS ACTIVITY:

SLAVE

ADDRESS

MASTER

SLAVE

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+2

DATA

BYTE

n+x

Figure 12. Sequential Read Sequence

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NV24C08LV

ORDERING INFORMATION

OPN

Density (Kb)

Package Type

Temperature Range

Shipping

NV24C08UVLT2G

US−8

V = Automotive Grade 1

Tape & Reel,

(−40°C to +125°C)

2,000 Units / Reel

NV24C08MUW3VLTBG

NV24C08DWVLT3G

NV24C08DTVLT3G

NV24C08SNVLT3G*

UDFN−8

Wettable Flank

V = Automotive Grade 1

(−40°C to +125°C)

Tape & Reel,

3,000 Units / Reel

SOIC−8

TSSOP−8

TSOP−5

V = Automotive Grade 1

(−40°C to +125°C)

Tape & Reel,

3,000 Units / Reel

V = Automotive Grade 1

(−40°C to +125°C)

Tape & Reel,

3,000 Units / Reel

V = Automotive Grade 1

(−40°C to +125°C)

Tape & Reel,

3,000 Units / Reel

9. All packages are RoHS−compliant (Lead−free, Halogen−free).

10.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*Product in development.

onsemi is licensed by Philips Corporation to carry the I C Bus Protocol.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSOP−5

CASE 483

ISSUE N

DATE 12 AUG 2020

SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

NOTE 5

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH

THICKNESS. MINIMUM LEAD THICKNESS IS THE

MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR GATE BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT

EXCEED 0.15 PER SIDE. DIMENSION A.

5. OPTIONAL CONSTRUCTION: AN ADDITIONAL

TRIMMED LEAD IS ALLOWED IN THIS LOCATION.

TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2

FROM BODY.

0.20 C A B

0.10

0.20

DETAIL Z

MILLIMETERS

TOP VIEW

DIM

MIN

2.85

1.35

0.90

0.25

MAX

3.15

1.65

1.10

0.50

DETAIL Z

0.95 BSC

0.01

0.10

0.20

0.10

0.26

0.60

3.00

0.05

SEATING

PLANE

END VIEW

SIDE VIEW

2.50

GENERIC

MARKING DIAGRAM*

SOLDERING FOOTPRINT*

1.9

0.074

0.95

XXXAYWG

XXX MG

0.037

Analog

Discrete/Logic

2.4

0.094

XXX = Specific Device Code XXX = Specific Device Code

= Assembly Location

= Year

= Work Week

= Date Code

= Pb−Free Package

1.0

0.039

= Pb−Free Package

(Note: Microdot may be in either location)

0.7

0.028

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

inches

SCALE 10:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ARB18753C

TSOP−5

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

US8

CASE 493

ISSUE F

DATE 01 SEP 2021

SCALE 4 :1

GENERIC

MARKING DIAGRAM*

XX MG

= Specific Device Code

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON04475D

US8

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

UDFN8 2x3, 0.5P

CASE 517DH

ISSUE A

SCALE 2:1

DATE 10 DEC 2020

GENERIC

MARKING DIAGRAM*

XXXXX = Specific Device Code

= Assembly Location

= Wafer Lot

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

= Year

XXXXX

= Work Week

= Pb−Free Package

AWLYWG

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON06579G

UDFN8 2X3, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−8, 150 mils

CASE 751BD

ISSUE O

DATE 19 DEC 2008

SYMBOL

MIN

NOM

MAX

1.35

1.75

0.10

0.33

0.19

4.80

5.80

3.80

0.25

0.51

0.25

5.00

6.20

4.00

1.27 BSC

0.25

0.40

0º

0.50

1.27

8º

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34272E

SOIC 8, 150 MILS

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP8, 4.4x3.0, 0.65P

CASE 948AL

ISSUE A

DATE 20 MAY 2022

GENERIC

MARKING DIAGRAM*

XXX

YWW

XXX = Specific Device Code

= Year

WW = Work Week

= Assembly Location

= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34428E

TSSOP8, 4.4X3.0, 0.65P

PAGE 1 OF 1

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