NV24C128MUW3VTBG [ONSEMI]

EEPROM Serial 128-Kb I2C - Automotive Grade;


型号：	NV24C128MUW3VTBG
厂家：	ONSEMI
描述：	EEPROM Serial 128-Kb I2C - Automotive Grade 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
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中文：	中文翻译
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EEPROM Serial 128-Kb I²C

Automotive Grade 1 in

Wettable Flank UDFN

Package

NV24C128MUW

www.onsemi.com

Description

The NV24C128MUW is a EEPROM Serial 128−Kb I2C

Automotive Grade 1, internally organized as 16,384 words of 8 bits

each.

UDFN8

MUW3 SUFFIX

CASE 517DH

It features a 64−byte page write buffer and supports both the

Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C

protocol.

Write operations can be inhibited by taking the WP pin High (this

protects the entire memory).

On−Chip ECC (Error Correction Code) makes the device suitable

for high reliability applications.

C7W

AWLYWG

Features

C7W

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified

• Supports Standard, Fast and Fast−Plus I C Protocol

• 2.5 V to 5.5 V Supply Voltage Range

• 64−Byte Page Write Buffer

= Pb−Free Package

• Hardware Write Protection for Entire Memory

PIN CONFIGURATION

• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs

(SCL and SDA)

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

SCL

SDA

• UDFN8 2 x 3 mm Wettable Flank Package

(Top View)

• This Device is Pb−Free, Halogen Free/BFR Free and RoHS

For the location of Pin 1, please consult the

corresponding package drawing.

Compliant*

PIN FUNCTION

Pin Name

Function

Device Address Inputs

Serial Data Input/Output

Serial Clock Input

Write Protect Input

Power Supply

SCL

A , A , A

SDA

A , A , A

NV24C128MU

SCL

Ground

Figure 1. Functional Symbol

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

* For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

July, 2020 − Rev. 3

NV24C128MUW/D

NV24C128MUW

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Units

°C

Storage Temperature

−65 to +150

−0.5 to +6.5

Voltage on Any Pin with Respect to Ground (Note 1)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

(Notes 3, 4)

Parameter

Min

1,000,000

100

Units

Program / Erase Cycles

Years

Endurance

END

Data Retention

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, V = 5 V, 25°C

4. This device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte

has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit

from the maximum number of write cycles.

Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise speciﬁed.)

Symbol

Parameter

Read Current

Test Conditions

= 400 kHz/1 MHz

SCL

Min

Max

Units

Read, f

CCR

Write Current

CCW

Standby Current

I/O Pin Leakage

Input Low Voltage

Input High Voltage

Output Low Voltage

All I/O Pins at GND or V

= −40°C to +125°C

T = −40°C to +125°C

Pin at GND or V

−0.5

0.3 V

0.7 V

+ 0.5

= 3.0 mA

0.4

Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise speciﬁed.)

Symbol

Parameter

Conditions

Max

Units

(Note 5)

SDA I/O Pin Capacitance

Input Capacitance (other pins)

WP Input Current, Address Input

= 0 V

, I (Note 6)

< V , V = 5.5 V

Current (A , A , A )

< V , V = 3.3 V

> V

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

6. When not driven, the WP, A , A , A pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively

strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,

as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.

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NV24C128MUW

Table 5. A.C. CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C) (Note 7)

Standard

Fast

Fast−Plus

Min

Max

Min

Max

Min

Max

Symbol

Parameter

Clock Frequency

Units

kHz

SCL

100

400

1,000

START Condition Hold Time

Low Period of SCL Clock

High Period of SCL Clock

START Condition Setup Time

Data In Hold Time

4.7

0.6

1.3

0.6

0.25

0.45

0.40

0.25

HD:STA

LOW

HIGH

4.7

SU:STA

HD:DAT

Data In Setup Time

250

100

SU:DAT

(Note 8)

SDA and SCL Rise Time

SDA and SCL Fall Time

STOP Condition Setup Time

1,000

300

100

(Note 8)

0.6

1.3

0.25

0.5

SU:STO

Bus Free Time Between

STOP and START

4.7

BUF

SCL Low to Data Out Valid

Data Out Hold Time

3.5

0.9

0.40

100

T (Note 8)

Noise Pulse Filtered at SCL

and SDA Inputs

100

WP Setup Time

SU:WP

WP Hold Time

2.5

HD:WP

Write Cycle Time

Power-up to Ready Mode

0.1

(Notes 8, 9)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Test conditions according to “A.C. Test Conditions” table.

8. Tested initially and after a design or process change that affects this parameter.

9. t is the delay between the time V is stable and the device is ready to accept commands.

Table 6. A.C. TEST CONDITIONS

Input Levels

0.2 x V to 0.8 x V

CC CC

Input Rise and Fall Times

Input Reference Levels

Output Reference Levels

Output Load

v 50 ns

0.3 x V , 0.7 x V

0.5 x V

Current Source: I = 3 mA; C = 100 pF

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NV24C128MUW

Power−On Reset (POR)

resistors. Master and Slave devices connect to the 2−wire

bus via their respective SCL and SDA pins. The transmitting

device pulls down the SDA line to ‘transmit’ a ‘0’ and

releases it to ‘transmit’ a ‘1’.

The NV24C128MUW incorporates Power−On Reset

(POR) circuitry which protects the device against powering

up in the wrong state.

The NV24C128MUW will power up into Standby mode

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

after V exceeds the POR trigger level and will power

down into Reset mode when V drops below the POR

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while SCL

is HIGH will be interpreted as a START or STOP condition

(Figure 2). The START condition precedes all commands. It

consists of a HIGH to LOW transition on SDA while SCL

is HIGH. The START acts as a ‘wake−up’ call to all

receivers. Absent a START, a Slave will not respond to

commands. The STOP condition completes all commands.

It consists of a LOW to HIGH transition on SDA while SCL

is HIGH.

trigger level. This bi−directional POR feature protects the

device against ‘brown−out’ failure following a temporary

loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master.

SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode, this pin

is open drain. Data is acquired on the positive edge, and is

delivered on the negative edge of SCL.

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. The first 4 bits of the Slave address are

set to 1010, for normal Read/Write operations (Figure 3).

The next 3 bits, A , A and A , select one of 8 possible Slave

A , A and A : The Address pins accept the device address.

When not driven, these pins are pulled LOW internally.

WP: The Write Protect input pin inhibits all write

operations, when pulled HIGH. When not driven, this pin is

pulled LOW internally.

devices and must match the state of the external address pins.

The last bit, R/W, specifies whether a Read (1) or Write (0)

operation is to be performed.

Functional Description

The NV24C128MUW supports the Inter−Integrated

Acknowledge

Circuit (I C) Bus data transmission protocol, which defines

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA line

a device that sends data to the bus as a transmitter and a

device receiving data as a receiver. Data flow is controlled

by a Master device, which generates the serial clock and all

START and STOP conditions. The NV24C128MUW acts as

a Slave device. Master and Slave alternate as either

transmitter or receiver. Up to 8 devices may be connected to

during the 9 clock cycle (Figure 4). The Slave will also

acknowledge all address bytes and every data byte presented

in Write mode. In Read mode the Slave shifts out a data byte,

and then releases the SDA line during the 9 clock cycle. As

long as the Master acknowledges the data, the Slave will

continue transmitting. The Master terminates the session by

not acknowledging the last data byte (NoACK) and by

issuing a STOP condition. Bus timing is illustrated in

Figure 5.

the bus as determined by the device address inputs A , A ,

and A .

I C Bus Protocol

The I C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the V supply via pull−up

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NV24C128MUW

SCL

SDA

START

CONDITION

STOP

CONDITION

Figure 2. START/STOP Conditions

DEVICE ADDRESS

R/W

Figure 3. Slave Address Bits

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (≥ t

)

SU:DAT

START

ACK DELAY (≤ t

)

Figure 4. Acknowledge Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

SU:DAT

SU:STO

HD:STA

SDA IN

BUF

SDA OUT

Figure 5. Bus Timing

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NV24C128MUW

Write Operations

and then wraps−around at the page boundary. Previously

loaded data can thus be overwritten by new data. What is

eventually written to memory reflects the latest Page Write

Buffer contents. Only data loaded within the most recent

Page Write sequence will be written to memory.

Byte Write

Upon receiving a Slave address with the R/W bit set to ‘0’,

the NV24C128MUW will interpret the next two bytes as

address bytes. These bytes are used to initialize the internal

address counter; the 2 most significant bits are ‘don’t care’,

the next 8 point to one of 256 available pages and the last 6

point to a location within a 64 byte page. A byte following

the address bytes will be interpreted as data. The data will be

loaded into the Page Write Buffer and will eventually be

written to memory at the address specified by the 14 active

address bits provided earlier. The NV24C128MUW will

acknowledge the Slave address, address bytes and data byte.

The Master then starts the internal Write cycle by issuing a

STOP condition (Figure 6). During the internal Write cycle

Acknowledge Polling

The ready/busy status of the NV24C128MUW can be

ascertained by sending Read or Write requests immediately

following the STOP condition that initiated the internal

Write cycle. As long as internal Write is in progress, the

NV24C128MUW will not acknowledge the Slave address.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the operation of

the NV24C128MUW. The state of the WP pin is strobed on

the last falling edge of SCL immediately preceding the first

data byte (Figure 9). If the WP pin is HIGH during the strobe

interval, the NV24C128MUW will not acknowledge the

data byte and the Write request will be rejected.

(t ), the SDA output will be tri−stated and additional Read

or Write requests will be ignored (Figure 7).

Page Write

By continuing to load data into the Page Write Buffer after

the 1 data byte and before issuing the STOP condition, up

to 64 bytes can be written simultaneously during one

internal Write cycle (Figure 8). If more data bytes are loaded

than locations available to the end of page, then loading will

continue from the beginning of page, i.e. the page address is

latched and the address count automatically increments to

Delivery State

The NV24C128MUW is shipped erased, i.e., all bytes are

FFh.

BUS ACTIVITY:

MASTER

ADDRESS

BYTE

ADDRESS

BYTE

a −a

7 0

DATA

BYTE

SLAVE

ADDRESS

−a

* *

SLAVE

* = Don’t Care Bit

Figure 6. Byte Write Sequence

SCL

SDA

8th Bit

Byte n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 7. Write Cycle Timing

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NV24C128MUW

BUS ACTIVITY:

MASTER

ADDRESS

BYTE

ADDRESS

BYTE

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+P

SLAVE

ADDRESS

−a

a −a

* *

SLAVE

* = Don’t Care Bit

P v 63

Figure 8. Page Write Sequence

ADDRESS

BYTE

DATA

BYTE

SCL

SDA

SU:WP

HD:WP

Figure 9. WP Timing

Read Operations

Immediate Read

with data, the Master instead follows up with an Immediate

Read sequence, then the NV24C128MUW will use the 14

active address bits to initialize the internal address counter

and will shift out data residing at the corresponding location.

If the Master does not acknowledge the data (NoACK) and

then follows up with a STOP condition (Figure 11), the

NV24C128MUW returns to Standby mode.

Upon receiving a Slave address with the R/W bit set to ‘1’,

the NV24C128MUW will interpret this as a request for data

residing at the current byte address in memory. The

NV24C128MUW will acknowledge the Slave address, will

immediately shift out the data residing at the current address,

and will then wait for the Master to respond. If the Master

does not acknowledge the data (NoACK) and then follows

Sequential Read

If during a Read session the Master acknowledges the 1

up with

STOP condition (Figure 10), the

data byte, then the NV24C128MUW will continue

transmitting data residing at subsequent locations until the

Master responds with a NoACK, followed by a STOP

(Figure 12). In contrast to Page Write, during Sequential

Read the address count will automatically increment to and

then wrap−around at end of memory (rather than end of

page).

NV24C128MUW returns to Standby mode.

Selective Read

To read data residing at a specific location, the internal

address counter must first be initialized as described under

Byte Write. If rather than following up the two address bytes

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NV24C128MUW

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA

BYTE

SLAVE

SCL

SDA

8th Bit

DATA OUT

NO ACK

STOP

Figure 10. Immediate Read Sequence and Timing

BUS ACTIVITY:

ADDRESS

BYTE

ADDRESS

BYTE

a −a

7 0

SLAVE

ADDRESS

SLAVE

ADDRESS

MASTER

−a

* *

DATA

BYTE

SLAVE

* = Don’t Care Bit

Figure 11. Selective Read Sequence

A T

C O

K P

BUS ACTIVITY:

SLAVE

ADDRESS

MASTER

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+2

DATA

BYTE

n+x

SLAVE

Figure 12. Sequential Read Sequence

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NV24C128MUW

ORDERING INFORMATION (Notes 10 thru 13)

Specific

Device

Marking

Package

Type

†

Device Order Number

Temperature Range

Lead Finish

Shipping

NV24C128MUW3VTBG

C7W

UDFN8 (2x3 mm)

Wettable Flank

V = Auto Grade 1

(−40°C to +125°C)

NiPdAu

Tape & Reel,

3,000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

10.All packages are RoHS−compliant (Lead−free, Halogen−free).

11. The standard lead finish is NiPdAu.

12.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

13.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com

ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

UDFN8 2x3, 0.5P

CASE 517DH

ISSUE A

SCALE 2:1

DATE 10 DEC 2020

GENERIC

MARKING DIAGRAM*

XXXXX = Specific Device Code

= Assembly Location

= Wafer Lot

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

= Year

XXXXX

= Work Week

= Pb−Free Package

AWLYWG

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON06579G

UDFN8 2X3, 0.5P

PAGE 1 OF 1

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For additional information, please contact your local Sales Representative at

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

NV24C128MUW3VTBG [ONSEMI]

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