NV24C256C6PTG [ONSEMI]
256 Kb I2C CMOS Serial EEPROM in WLCSP Package;型号: | NV24C256C6PTG |
厂家: | ONSEMI |
描述: | 256 Kb I2C CMOS Serial EEPROM in WLCSP Package 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总9页 (文件大小:131K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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256 Kb I2C CMOS Serial
EEPROM in WLCSP Package
WLCSP6
C6PTG SUFFIX
CASE 567ZZ
NV24C256C6PTG
Description
The NV24C256C6PTG is a 256 Kb Serial CMOS EEPROM,
internally organized as 32768 words of 8 bits each.
They feature a 64-byte page write buffer and support both the
Standard (100 kHz), Fast (400 kHz) and Fast-Plus (1 MHz) I C
protocol.
The Write Protect input allows hardware protection for the memory
array. The A2 input allows two NV24C256C6PTG devices to be
connected to the same bus.
PIN CONFIGURATION
1
2
3
2
Pin 1
A
B
WP
A2
SDA
V
CC
SCL
V
SS
Features
(Top View)
2
• Supports Standard, Fast and Fast-Plus I C Protocol
2
PIN FUNCTION
• Two Selectable I C Device Addresses
• 1.7 V to 5.5 V Supply Voltage Range
• 64-byte Page Write Buffer
Pin Name
SDA
Function
Serial Data Input/Output
Serial Clock Input
Power Supply
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
SCL
(SCL and SDA)
V
CC
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
V
Ground
SS
WP
A2
Hardware Write Protect
Address Pin
• Automotive Temperature Range: −40°C to +105°C
• Ultra-thin 6-ball WLCSP Package
MARKING DIAGRAM
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant*
U
AYWW
V
CC
A2
WP
U
A
Y
= Specific Device Code
= Assembly Location
= Production Year
SDA
WW = Production Week
SCL
V
SS
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
NV24C256C6PTG
Figure 1. Functional Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the onsemi Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
May, 2022 − Rev. 0
NV24C256C6PTG/D
NV24C256C6PTG
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 1.0 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Unit
Program/Erase Cycles
Years
N
Endurance
END
T
(Note 4)
Data Retention
DR
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25_C
CC
4. T = 55_C
A
Table 3. DC AND AC OPERATING CONDITIONS
Supply Voltage / Temperature Range
Operation
READ / WRITE
READ
V
CC
V
CC
V
CC
= 1.7 V to 5.5 V / T = −40°C to +105°C
A
= 1.6 V to 5.5 V / T = −40°C to +105°C
A
= 1.6 V to 5.5 V / T = 0°C to +105°C
WRITE
A
Table 4. D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Unit
mA
mA
mA
Read, f
= 400 kHz/1 MHz
Read Current
1
I
SCL
CCR
Write Current
2
I
CCW
All I/O Pins at GND or V
V
V
< 2.5 V
Standby Current
1
2
I
SB
CC
CC
> 2.5 V
CC
Pin at GND or V
I/O Pin Leakage
2
mA
V
I
CC
L
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
≥ 2.5 V
< 2.5 V
≥ 2.5 V
< 2.5 V
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
−0.5
0.3 V
V
V
V
CC
IL1
IL2
0.25 V
V
CC
0.7 V
V
+ 1
V
CC
CC
CC
IH1
IH2
0.75 V
V
+ 1
V
V
CC
0.4
0.2
V
V
≥ 2.5 V, I = 3.0 mA
OL1
OL
V
V
< 2.5 V, I = 1.0 mA
OL2
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 5. PIN IMPEDANCE CHARACTERISTICS
Symbol
Parameter
Conditions
Max
8
Unit
pF
C
C
(Note 5)
(Note 5)
SDA I/O Pin Capacitance
Input Capacitance (other pins)
V
V
= 0 V
= 0 V
IN
IN
IN
6
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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2
NV24C256C6PTG
Table 6. A.C. CHARACTERISTICS (Note 6)
Standard
Fast
= 1.7 to 5.5
Fast−Plus
V = 1.7 to 5.5
CC
V
= 1.7 to 5.5
V
CC
CC
T
= −40 to 1055C
T
= −40 to 1055C
T
= −40 to 1055C
A
A
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
kHz
ms
Clock Frequency
100
400
1,000
F
SCL
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
0.6
0.25
t
HD:STA
ms
4.7
4
1.3
0.6
0.6
0
0.45
0.40
0.25
0
t
LOW
ms
t
HIGH
ms
4.7
0
t
SU:STA
HD:DAT
ms
t
ns
Data In Setup Time
250
100
20
50
t
SU:DAT
ns
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
1,000
300
300
300
100
100
R
ns
t (Note 7)
F
20
ms
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
4
0.6
1.3
0.25
0.5
t
SU:STO
ms
4.7
t
BUF
ms
3.5
0.9
0.40
t
AA
ns
100
100
50
t
DH
ns
T (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
100
5
50
5
50
5
i
ms
ms
t
WR
Power-up to Ready Mode
0.35
0.35
0.35
T
PU
(Notes 7, 8)
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 7. A.C. TEST CONDITIONS
Parameter
Condition
Input Levels
0.2 × V to 0.8 × V
CC CC
≤ 50 ns
0.3 × V , 0.7 × V
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
CC
CC
0.5 × V
CC
Current Source: I = 3 mA (V ≥ 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
Output Load
OL
CC
OL
CC
L
V
CC
10
1
R
P
300 ns Rise Time
SDA
120 ns Rise Time
C
L
V
SS
0.1
100
Load Capacitance (pF)
10
Figure 2. Maximum Pull-up Resistance vs. Load Capacitance
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3
NV24C256C6PTG
Power-On Reset (POR)
resistors. Master and Slave devices connect to the 2-wire bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
The NV24C256C6PTG incorporates Power-On Reset
(POR) circuitry which protects the device against powering
up in the wrong state.
The NV24C256C6PTG will power up into Standby mode
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
after V exceeds the POR trigger level and will power down
CC
into Reset mode when V drops below the POR trigger
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake-up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
CC
level. This bi-directional POR feature protects the device
against ‘brown-out’ failure following a temporary loss of
power.
Pin Description
• SCL: The Serial Clock input pin accepts the Serial
Clock generated by the Master.
• SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
• WP: WP is the Write Protect pin. While the WP pin is
connected to the power supply, the entire array becomes
Write Protected (i.e. the device becomes Read only).
When WP is tied to Ground or left floating, the normal
write operations are allowed.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010. The next 3 bits must match the logic state of A2,
0 and 0. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
• A2: The A2 pin is a device address input. If A2 is left
floating, the input defaults to zero. When A2 is set to
logic−0 the device address is 0xA1/0xA0 for read/write.
When A2 is set to logic−1 the device address is
0xA9/0xA8 for read/write.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
th
during the 9 clock cycle (Figure 5). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode if the addressed location is not write
protected. In Read mode the Slave shifts out a data byte, and
Functional Description
The NV24C256C6PTG supports the Inter-Integrated
th
2
then releases the SDA line during the 9 clock cycle. As
Circuit (I C) Bus data transmission protocol, which defines
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 6.
a device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock and all
START and STOP conditions. The NV24C256C6PTG acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C Bus Protocol
2
The I C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V supply via pull-up
CC
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 3. START/STOP Conditions
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NV24C256C6PTG
Memory Array Access
1
0
1
0
A2
0
0
R/W
Figure 4. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 5. Acknowledge Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
t
DH
AA
SDA OUT
Figure 6. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be written
(Figure 7). The Slave, NV24C256C6PTG acknowledges all
4 bytes, and the Master then follows up with a STOP, which
in turn starts the internal Write operation (Figure 8). During
from the address active bits (a14 to a6) identify the page and
the last 6 bits (a5 to a0) identify the byte within the page. Up
to 64 bytes can be written in one Write cycle (Figure 9). The
internal byte address counter is automatically incremented
after each data byte is loaded. If the Master transmits more
than 64 data bytes, then earlier bytes will be overwritten by
later bytes in a ‘wrap-around’ fashion (within the selected
page). The internal Write cycle starts immediately following
the STOP.
the internal Write cycle (t ), the NV24C256C6PTG will
not acknowledge any Read or Write request from the Master.
WR
Acknowledge Polling
Page Write
The ready/busy status of the NV24C256C6PTG can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
NV24C256C6PTG will not acknowledge the Slave address.
The NV24C256C6PTG contains 32,768 bytes of data,
arranged in 512 pages of 64 bytes each. A two byte address
word, following the Slave address, points to the first byte to
be written into the memory array. The most significant 9 bits
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5
NV24C256C6PTG
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
−a
ADDRESS
BYTE
a −a
7 0
S
T
O
P
DATA
BYTE
SLAVE
ADDRESS
a
14
8
S
*
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
Figure 7. Byte Write Sequence
SCL
SDA
ACK
8th Bit
Byte n
t
WR
ADDRESS
STOP
CONDITION
START
CONDITION
Figure 8. Write Cycle Timing
BUSACTIVITY: S
ADDRESS
BYTE
ADDRESS
BYTE
a −a
7 0
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
T
A
S
T
SLAVE
R
O
P
ADDRESS
MASTER
a
−a
14
8
T
S
*
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
P ≤ 63
Figure 9. Page Write Sequence
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6
NV24C256C6PTG
Read Operations
active address bits to initialize the internal address counter
and will shift out data residing at the corresponding location.
If the Master does not acknowledge the data (NoACK) and
then follows up with a STOP condition (Figure 11), the
NV24C256C6PTG returns to Standby mode.
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the NV24C256C6PTG will interpret this as a request for
data residing at the current byte address in memory. The
NV24C256C6PTG will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 10), the
NV24C256C6PTG returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1
st
data byte, then the NV24C256C6PTG will continue
transmitting data residing at subsequent locations until the
Master responds with a NoACK, followed by a STOP
(Figure 12). In contrast to Page Write, during Sequential
Read the address count will automatically increment to and
then wrap-around at end of memory (rather than end of
page).
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
with data, the Master instead follows up with an Immediate
Read sequence, then the NV24C256C6PTG will use the 15
Delivery State
The NV24C256C6PTG is shipped erased, i.e., all
memory array bytes are FFh.
N
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
O
SLAVE
ADDRESS
A
C
K
O
P
S
P
A
C
K
DATA
SLAVE
8
BYTE
9
SCL
SDA
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVIT Y:
MASTER
S
T
S
N
O
A
C
K
T
A
R
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
A
R
SLAVE
ADDRESS
SLAVE
ADDRESS
a
−a
14
a −a
0
8
7
T
T
S
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Selective Read Sequence
N
BUS ACTIVITY:
MASTER
O
S
SLAVE
ADDRESS
A T
O
C
K P
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
n+2
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
SLAVE
Figure 12. Sequential Read Sequence
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NV24C256C6PTG
Table 8. ORDERING INFORMATION (Notes 9 thru 11)
Device
Order Number
Specific
Device Marking
Package
Type
Temperature
Range
†
Bump Composition
Shipping
NV24C256C6PTG
U
WLCSP 6-ball
Automotive
(−40°C to +105°C)
CuNiSnAg
5,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. All packages are RoHS-compliant (Lead-free, Halogen-free).
10.For detailed information and a breakdown of device nomenclature and numbering systems, please see the onsemi Device Nomenclature
document, TND310/D, available at www.onsemi.com
11. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light the
EEPROM cells lose their stored data.
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NV24C256C6PTG
PACKAGE DIMENSIONS
WLCSP6 1.11x0.98x0.35
CASE 567ZZ
ISSUE O
2
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