NV24C32DTVLT3G [ONSEMI]
EEPROM 串行 32-Kb I2C - 汽车级;
| 型号： | NV24C32DTVLT3G |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM 串行 32-Kb I2C - 汽车级 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总13页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EEPROM Serial 32-Kb I2C
- Automotive Grade 1
NV24C32LV
Description
The NV24C32LV is a 32 Kb CMOS Serial EEPROM device,
organized internally as 128 pages of 32 bytes each. This device
supports the Standard (100 kHz), Fast (400 kHz) and Fast−Plus
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2
(1 MHz) I C protocol.
Data is written by providing a starting address, then loading 1 to 32
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
1
US8
U SUFFIX
CASE 493
UDFN−8
MUW3 SUFFIX
CASE 517DH
External address pins make it possible to address up to eight
NV24C32LV devices on the same bus.
8
Features
1
SOIC−8
DW SUFFIX
CASE 751BD
TSSOP−8
DT SUFFIX
CASE 948AL
• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified
2
• Supports Standard, Fast and Fast−Plus I C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Fast Write Time (4 ms max)
PIN CONFIGURATION
• Hardware Write Protection for Entire Memory
1
V
CC
A
0
A
1
A
2
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
WP
(SCL and SDA)
SCL
SDA
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
V
SS
(Top View)
• Automotive Grade 1 Temperature Range
• US−8, UDFN−8, SOIC−8 and TSSOP−8 Packages
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 13 of this data sheet.
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
November, 2019 − Rev. 1
NV24C32LV/D
NV24C32LV
V
CC
SCL
NV24C32LV
SDA
A , A , A
2
1
0
WP
V
SS
PIN FUNCTION
Pin Name
Function
A , A , A
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
0
1
2
SDA
SCL
WP
V
CC
V
SS
Figure 1. Functional Symbols
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
–65 to +150
–0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS
Symbol
(Note 2)
Parameter
Max
1,000,000
100
Units
Write Cycles (Note 3)
Years
N
Endurance
END
T
(Note 2)
Data Retention
DR
2. T = 25°C
A
3. A Write Cycle refers to writing a Byte or a Page.
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2
NV24C32LV
Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
mA
mA
mA
mA
V
I
Read Current
Write Current
Read, f
= 1 MHz
= 1 MHz
1
1
2
2
CCR
SCL
SCL
I
Write, f
CCW
I
SB
Standby Current
All I/O Pins at GND or V
CC
I
L
I/O Pin Leakage
Pin at GND or V
SCL, SDA
CC
V
IL
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
V
x 0.3
CC
V
IH
SCL, SDA
V
x 0.7
CC
V
+ 0.5
x 0.3
+ 0.5
V
CC
V
A2, A1, A0 and WP
A2, A1, A0 and WP
−0.5
x 0.8
V
V
ILA
IHA
OL1
OL2
CC
CC
V
V
V
V
CC
V
V
V
CC
V
CC
≥ 2.5 V, I = 3.0 mA
0.4
0.2
V
OL
< 2.5 V, I = 1.0 mA
V
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
Conditions
Min
Max
8
Units
pF
C
C
(Note 4)
(Note 4)
(Note 5)
(Note 5)
V
IN
V
IN
V
IN
V
IN
= 0 V
= 0 V
IN
IN
6
pF
R
WP, A0, A1 or A2 On−Chip Pull−Down Resistor
WP, A0, A1 or A2 On−Chip Pull−Down Current
< V
> V
50
kW
PD
PD
IHA
IHA
I
2
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. For improved noise immunity (and to allow for floating input pins), the WP, A0, A1 & A2 inputs are pulled−down to GND by relatively strong
on−chip resistors. When attempting to drive these inputs High, the external drivers must be able to supply sufficient current, until the input level
at the pin exceeds V . Once the input level at the pin exceeds V , the resistive pull−down (R ) converts to a constant current pull−down
IHA
IHA
PD
(I ).
PD
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3
NV24C32LV
Table 5. A.C. CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +125°C unless otherwise noted.) (Note 6)
CC
A
Standard
Fast
Fast−Plus
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Clock Frequency
Units
kHz
ms
F
SCL
100
400
1,000
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
0.25
0.45
0.40
0.25
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
50
ns
SU:DAT
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1,000
300
300
300
100
100
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
0.25
0.5
ms
SU:STO
t
Bus Free Time Between
STOP and START
4.7
ms
BUF
t
SCL Low to Data Out Valid
Data Out Hold Time
3.5
50
0.9
50
0.40
50
ms
ns
ns
AA
t
(Note 7)
100
100
50
DH
T (Note 7)
Noise Pulse Filtered at SCL
and SDA Inputs
i
t
WP Setup Time
0
0
0
1
ms
ms
SU:WP
t
WP Hold Time
2.5
2.5
HD:WP
t
Write Cycle Time
Power-up to Ready Mode
4
4
4
ms
ms
WR
t
(Notes 7, 8)
0.35
0.35
0.35
PU
*V
CC(min)
= 1.6 V for Read operations, T = −20°C to +85°C
A
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V for V ≥ 2.2 V; 0.15 x V to 0.85 x V for V < 2.2 V
CC
CC
CC
CC
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
≤ 50 ns
0.3 x V , 0.7 x V
CC
CC
0.3 x V , 0.7 x V
CC
CC
Current Source: I = 6 mA (V ≥ 2.5 V); I = 2 mA (V < 2.5 V); C = 100 pF
OL
CC
OL
CC
L
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4
NV24C32LV
I2C Bus Protocol
The 2-wire I C bus consists of two lines, SCL and SDA,
connected to the V supply via pull-up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
Power-On Reset (POR)
2
Each NV24C32LV incorporates Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
CC
mode after V exceeds the POR trigger level and will
CC
power down into Reset mode when V drops below the
CC
POR trigger level. This bi-directional POR behavior
protects the device against ‘brown-out’ failure following a
temporary loss of power.
START/STOP Condition
Pin Description
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
Device Addressing
A , A and A : The Address inputs set the device address
0
1
2
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address. For
the NV24C32LV, the first four bits of the Slave address are
that must be matched by the corresponding Slave address
bits. The Address inputs are hard-wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these inputs are pulled LOW
internally.
set to 1010 (Ah); the next three bits, A , A and A , must
2
1
0
match the logic state of the similarly named input pins. The
R/W bit tells the Slave whether the Master intends to read (1)
or write (0) data (Figure 3).
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally.
Acknowledge
During the 9 clock cycle following every byte sent to the
th
Functional Description
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
The NV24C32LV supports the Inter-Integrated Circuit
2
(I C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The NV24C32LV
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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5
NV24C32LV
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Acknowledge Timing
t
F
t
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow-up with a new Read or
Write request, rather than wait for the maximum specified
Write time (t ) to elapse. Upon receiving a NoACK
WR
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
operation is in progress (t ), the SDA output is tri-stated
and the Slave does not acknowledge the Master (Figure 7).
WR
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
st
falling edge of SCL immediately preceding the 1 data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The NV24C32LV is shipped erased, i.e., all bytes are FFh.
written to memory in a single internal Write cycle (t ).
WR
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6
NV24C32LV
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
SLAVE
O
P
ADDRESS
a
15
− a
a
7
− a
d − d
7 0
8
0
S
P
* * * *
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
*a − a are don’t care bits.
15
12
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
START
ADDRESS
CONDITION
CONDITION
Figure 7. Write Cycle Timing
BUS
ACTIVITY: S
T
A
S
T
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
SLAVE
ADDRESS
ADDRESS
BYTE
ADDRESS
BYTE
MASTER
R
T
O
P
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
A
A
C
K
SLAVE
C
K
C
K
n = 1; P ≤ 31
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
1
8
9
8
d
SCL
a
a
0
d
7
SDA
WP
7
0
t
SU:WP
t
HD:WP
Figure 9. WP Timing
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7
NV24C32LV
READ OPERATIONS
Immediate Read
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
N
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
DATA
C
SLAVE
8
BYTE
K
SCL
SDA
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
N
O
BUS ACTIVITY:
S
T
A
R
T
S
T
A
S
T
A
C
K
ADDRESS
BYTE
ADDRESS
BYTE
SLAVE
SLAVE
MASTER
R
T
O
P
ADDRESS
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
DATA
BYTE
Figure 11. Selective Read Sequence
N
O
A
C
K
BUS ACTIVITY:
MASTER
S
T
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
O
P
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
US8
CASE 493
ISSUE F
DATE 01 SEP 2021
SCALE 4 :1
GENERIC
MARKING DIAGRAM*
8
XX MG
G
1
XX
M
= Specific Device Code
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04475D
US8
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2021
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8 2x3, 0.5P
CASE 517DH
ISSUE A
1
SCALE 2:1
DATE 10 DEC 2020
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
*This information is generic. Please refer to
1
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
= Year
XXXXX
W
G
= Work Week
= Pb−Free Package
AWLYWG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON06579G
UDFN8 2X3, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX = Specific Device Code
Y
= Year
WW = Work Week
A
G
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
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