NV24C64DTUTG [ONSEMI]

64 Kb I2C CMOS Serial EEPROM;


型号：	NV24C64DTUTG
厂家：	ONSEMI
描述：	64 Kb I2C CMOS Serial EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总11页 (文件大小：107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NV24C64

Product Preview

64 Kb I²C CMOS Serial

EEPROM

Description

www.onsemi.com

The NV24C64 is a 64 Kb CMOS Serial EEPROM device, internally

organized as 8192 words of 8 bits each.

It features a 32−byte page write buffer and supports the Standard

(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C protocol.

External address pins make it possible to address up to eight

NV24C64 devices on the same bus.

SOIC−8

DW SUFFIX

CASE 751BD

TSSOP−8

DT SUFFIX

CASE 948AL

WLCSP−4

C4 SUFFIX

CASE 567JY

Features

• Supports Standard, Fast and Fast−Plus I C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 32−Byte Page Write Buffer

PIN CONFIGURATIONS (Top Views)

• Hardware Write Protection for Entire Memory

• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs

(SCL and SDA)

SCL

SDA

SCL

SDA

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

SOIC (DW), TSSOP (DT)

WLCSP (C4)

For the location of Pin 1, please consult the

corresponding package drawing.

• Automotive Grade 2 (105°C) Temperature Range

• SOIC, TSSOP 8−lead and WLCSP 4−bump Packages

• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS

Compliant

PIN FUNCTION

Pin Name

Function

Device Address

A , A , A

SDA

Serial Data

Serial Clock

Write Protect

Power Supply

Ground

SCL

NV24C64

SDA

A , A , A

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 11 of this data sheet.

Figure 1. Functional Symbol

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

Publication Order Number:

August, 2016 − Rev. P1

NV24C64/D

NV24C64

MARKING DIAGRAMS

T64F

AYMXXX

W64F

AYMXXX

(WLCSP−4)

(TSSOP−8)

= Specific Device Code

= Production Year

= Work Week

T64F

= Specific Device Code

= Assembly Location

XXX

= Production Year (Last Digit)

= Production Month (1−9, O, N, D)

= Last Three Digits of

(SOIC−8)

W64F = Specific Device Code

= Assembly Lot Number

= Pb−Free Microdot

= Assembly Location

= Production Year (Last Digit)

= Production Month (1−9, O, N, D)

XXX = Last Three Digits of

XXX = Assembly Lot Number

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

Units

Storage Temperature

–65 to +150

–0.5 to +6.5

°C

Voltage on Any Pin with Respect to Ground (Note 1)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

(Note 3)

Parameter

Min

1,000,000

100

Units

Program/Erase Cycles

Years

Endurance

END

Data Retention

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, V = 5 V, 25°C.

Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +105°C, unless otherwise speciﬁed.)

Symbol

Parameter

Test Conditions

Min

Max

Units

Read Current

Write Current

Read, f

= 1 MHz

CCR

SCL

Write, f

CCW

Standby Current

All I/O Pins at GND or V

I/O Pin Leakage

Pin at GND or V

SCL, SDA

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

−0.5

x 0.3

SCL, SDA

x 0.7

+ 0.5

x 0.3

+ 0.5

ILA

A2, A1, A0 and WP

−0.5

x 0.8

IHA

≥ 2.5 V, I = 3.0 mA

0.4

0.2

OL1

OL2

< 2.5 V, I = 1.0 mA

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NV24C64

Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +105°C, unless otherwise speciﬁed.)

Symbol

Parameter

SDA I/O Pin Capacitance

Input Capacitance (other pins)

Conditions

Min

Max

Units

(Note 4)

(Note 5)

= 0 V

WP, A0, A1 or A2 On−Chip Pull−Down Resistor

WP, A0, A1 or A2 On−Chip Pull−Down Current

< V

> V

IHA

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. For improved noise immunity (and to allow for floating input pins), the WP, A0, A1 & A2 inputs are pulled−down to GND by relatively strong

on−chip resistors. When attempting to drive these inputs High, the external drivers must be able to supply sufficient current, until the input level

at the pin exceeds V . Once the input level at the pin exceeds V , the resistive pull−down (R ) converts to a constant current pull−down

IHA

(I ).

Table 5. A.C. CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to +105°C) (Note 6)

Standard

Fast

Fast−Plus

Min

Max

Min

Max

Min

Max

Symbol

Parameter

Clock Frequency

Units

kHz

SCL

100

400

1,000

START Condition Hold Time

Low Period of SCL Clock

High Period of SCL Clock

START Condition Setup Time

Data In Hold Time

4.7

0.6

1.3

0.6

0.25

0.45

0.40

0.25

HD:STA

LOW

HIGH

4.7

SU:STA

HD:DAT

Data In Setup Time

250

100

SU:DAT

(Note 7)

SDA and SCL Rise Time

SDA and SCL Fall Time

STOP Condition Setup Time

1,000

300

100

t (Note 7)

0.6

1.3

0.25

0.5

SU:STO

Bus Free Time Between

STOP and START

4.7

BUF

SCL Low to Data Out Valid

Data Out Hold Time

3.5

0.9

0.40

100

T (Note 7)

Noise Pulse Filtered at SCL

and SDA Inputs

100

WP Setup Time

SU:WP

WP Hold Time

2.5

HD:WP

Write Cycle Time

Power−up to Ready Mode

(Notes 7, 8)

0.1

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

8. t is the delay between the time V is stable and the device is ready to accept commands.

Table 6. A.C. TEST CONDITIONS

Input Levels

0.2 x V to 0.8 x V for V > 2.2 V and 0.15 x V to 0.85 x V for V < 2.2 V

Input Rise and Fall Times

Input Reference Levels

Output Reference Levels

Output Load

≤ 50 ns

0.3 x V , 0.7 x V

0.5 x V

Current Source: I = 3 mA (V ≥ 2.2 V); I = 1 mA (V < 2.2 V); C = 100 pF

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NV24C64

Power−On Reset (POR)

transmit or receive, but only the Master can assign those

Each NV24C64 incorporates Power−On Reset (POR)

circuitry which protects the internal logic against powering

up in the wrong state. The device will power up into Standby

roles.

I²C Bus Protocol

The 2−wire I C bus consists of two lines, SCL and SDA,

connected to the V supply via pull−up resistors. The

mode after V exceeds the POR trigger level and will

power down into Reset mode when V drops below the

Master provides the clock to the SCL line, and either the

Master or the Slaves drive the SDA line. A ‘0’ is transmitted

by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data

transfer may be initiated only when the bus is not busy (see

A.C. Characteristics). During data transfer, SDA must

remain stable while SCL is HIGH.

POR trigger level. This bi−directional POR behavior

protects the device against ‘brown−out’ failure following a

temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the clock signal

generated by the Master.

START/STOP Condition

SDA: The Serial Data I/O pin accepts input data and delivers

output data. In transmit mode, this pin is open drain. Data is

acquired on the positive edge, and is delivered on the

negative edge of SCL.

An SDA transition while SCL is HIGH creates a START

or STOP condition (Figure 2). The START consists of a

HIGH to LOW SDA transition, while SCL is HIGH. Absent

the START, a Slave will not respond to the Master. The

STOP completes all commands, and consists of a LOW to

HIGH SDA transition, while SCL is HIGH.

A , A and A : The Address inputs set the device address

that must be matched by the corresponding Slave address

bits. The Address inputs are hard−wired HIGH or LOW

allowing for up to eight devices to be used (cascaded) on the

same bus. When left floating, these pins are pulled LOW

internally. The Address inputs are not available for use with

WLCSP 4−bumps.

Device Addressing

The Master addresses a Slave by creating a START

condition and then broadcasting an 8−bit Slave address. For

the NV24C64, the first four bits of the Slave address are set

to 1010 (Ah); the next three bits, A , A and A , must match

WP: When pulled HIGH, the Write Protect input pin

inhibits all write operations. When left floating, this pin is

pulled LOW internally. The WP input is not available for the

WLCSP 4−bumps, therefore all write operations are allowed

for the device in this package.

the logic state of the similarly named input pins. The devices

in WLCSP 4−bumps respond only to the Slave Address with

A2 A1 A0 = 000 (NV24C64C4CTR) or to A2 A1 A0 = 100

(NV24C64AC4CTR). The R/W bit tells the Slave whether

the Master intends to read (1) or write (0) data (Figure 3).

Functional Description

The NV24C64 supports the Inter−Integrated Circuit (I C)

Acknowledge

During the 9 clock cycle following every byte sent to the

Bus protocol. The protocol relies on the use of a Master

device, which provides the clock and directs bus traffic, and

Slave devices which execute requests. The NV24C64

operates as a Slave device. Both Master and Slave can

bus, the transmitter releases the SDA line, allowing the

receiver to respond. The receiver then either acknowledges

(ACK) by pulling SDA LOW, or does not acknowledge

(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing

is illustrated in Figure 5.

SCL

SDA

START

STOP

CONDITION

Figure 2. Start/Stop Timing

R/W

DEVICE ADDRESS*

* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 000, NV24C64C4UX4TG

Figure 3. Slave Address Bits

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NV24C64

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (≥ t

)

SU:DAT

START

ACK DELAY (≤ t

)

Figure 4. Acknowledge Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

SU:DAT

SU:STO

HD:STA

SDA IN

BUF

SDA OUT

Figure 5. Bus Timing

WRITE OPERATIONS

Byte Write

Acknowledge Polling

To write data to memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘0’. The Master then sends two

address bytes and a data byte and concludes the session by

creating a STOP condition on the bus. The Slave responds

with ACK after every byte sent by the Master (Figure 6). The

STOP starts the internal Write cycle, and while this

As soon (and as long) as internal Write is in progress, the

Slave will not acknowledge the Master. This feature enables

the Master to immediately follow−up with a new Read or

Write request, rather than wait for the maximum specified

Write time (t ) to elapse. Upon receiving a NoACK

response from the Slave, the Master simply repeats the

request until the Slave responds with ACK.

operation is in progress (t ), the SDA output is tri−stated

and the Slave does not acknowledge the Master (Figure 7).

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the Write

operation. The state of the WP pin is strobed on the last

Page Write

The Byte Write operation can be expanded to Page Write,

by sending more than one data byte to the Slave before

issuing the STOP condition (Figure 8). Up to 32 distinct data

bytes can be loaded into the internal Page Write Buffer

starting at the address provided by the Master. The page

address is latched, and as long as the Master keeps sending

data, the internal byte address is incremented up to the end

of page, where it then wraps around (within the page). New

data can therefore replace data loaded earlier. Following the

STOP, data loaded during the Page Write session will be

falling edge of SCL immediately preceding the 1 data byte

(Figure 9). If the WP pin is HIGH during the strobe interval,

the Slave will not acknowledge the data byte and the Write

request will be rejected.

Delivery State

The NV24C64 is shipped erased, i.e., all bytes are FFh.

written to memory in a single internal Write cycle (t ).

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NV24C64

BUS ACTIVITY:

MASTER

ADDRESS

BYTE

ADDRESS

BYTE

DATA

BYTE

SLAVE

ADDRESS

− a

a − a

d − d

7 0

* * *

SLAVE

*a − a are don’t care bits.

Figure 6. Byte Write Sequence

SCL

SDA

8th Bit

Byte n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 7. Write Cycle Timing

BUS

ACTIVITY: S

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+P

SLAVE

ADDRESS

BYTE

ADDRESS

BYTE

MASTER

SLAVE

Figure 8. Page Write Sequence

ADDRESS

BYTE

DATA

BYTE

SCL

SDA

SU:WP

HD:WP

Figure 9. WP Timing

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NV24C64

READ OPERATIONS

Immediate Read

Write sequence by sending data, the Master then creates a

START condition and broadcasts a Slave address with the

R/W bit set to ‘1’. The Slave responds with ACK after every

byte sent by the Master and then sends out data residing at

the selected address. After receiving the data, the Master

responds with NoACK and then terminates the session by

creating a STOP condition on the bus (Figure 11).

To read data from memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘1’. The Slave responds with ACK

and starts shifting out data residing at the current address.

After receiving the data, the Master responds with NoACK

and terminates the session by creating a STOP condition on

the bus (Figure 10). The Slave then returns to Standby mode.

Sequential Read

Selective Read

If, after receiving data sent by the Slave, the Master

responds with ACK, then the Slave will continue

transmitting until the Master responds with NoACK

followed by STOP (Figure 12). During Sequential Read the

internal byte address is automatically incremented up to the

end of memory, where it then wraps around to the beginning

of memory.

To read data residing at a speciﬁc address, the selected

address must ﬁrst be loaded into the internal address register.

This is done by starting a Byte Write sequence, whereby the

Master creates a START condition, then broadcasts a Slave

address with the R/W bit set to ‘0’ and then sends two

address bytes to the Slave. Rather than completing the Byte

BUS ACTIVITY:

MASTER

A T

C O

K P

SLAVE

ADDRESS

DATA

SLAVE

BYTE

SCL

SDA

8th Bit

DATA OUT

NO ACK

STOP

Figure 10. Immediate Read Sequence and Timing

BUS ACTIVITY:

ADDRESS

BYTE

ADDRESS

BYTE

SLAVE

ADDRESS

SLAVE

ADDRESS

MASTER

SLAVE

DATA

BYTE

Figure 11. Selective Read Sequence

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SLAVE

DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+2

DATA

BYTE

n+x

Figure 12. Sequential Read Sequence

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NV24C64

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

SYMBOL

MIN

NOM

MAX

1.35

1.75

0.25

0.51

0.25

0.10

0.33

0.19

4.80

5.80

3.80

5.00

6.20

4.00

1.27 BSC

0.25

0.40

0º

0.50

1.27

8º

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

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NV24C64

PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

SYMBOL

MIN

NOM

MAX

1.20

0.15

1.05

0.30

0.20

3.10

6.50

4.50

0.05

0.80

0.19

0.09

2.90

6.30

4.30

0.90

3.00

6.40

4.40

0.65 BSC

1.00 REF

0.60

0.50

0.75

0º

8º

TOP VIEW

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

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NV24C64

PACKAGE DIMENSIONS

WLCSP4, 0.77x0.77

CASE 567JY

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF

THE SOLDER BALLS.

PIN A1

REFERENCE

5. DIMENSION b IS MEASURED AT THE MAXIMUM

CONTACT BALL DIAMETER PARALLEL TO DATUM C.

6. BACKSIDE COATING IS OPTIONAL.

TOP VIEW

NOTE 6

DIE COAT

(OPTIONAL)

MILLIMETERS

DIM

MIN

−−−

0.04

NOM

−−−

0.055

0.255 REF

0.025 REF

0.155

MAX

0.35

0.07

DETAIL A

0.05

DETAIL A

0.15

0.75

0.16

0.79

NOTE 3

0.05

0.77

SEATING

PLANE

NOTE 4

0.40 BSC

SIDE VIEW

RECOMMENDED

NOTE 5

SOLDERING FOOTPRINT*

PACKAGE

OUTLINE

0.05

0.03

A B

BOTTOM VIEW

0.40

PITCH

0.16

0.40

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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NV24C64

ORDERING INFORMATION

Specific

Device

Marking

Device Order Number

Package Type

Temperature Range

Lead Finish

Shipping

NV24C64DWUTG

W64F

T64F

SOIC−8, JEDEC

(−40°C to +105°C)

NiPdAu

Tape & Reel,

3,000 Units / Reel

NV24C64DTUTG

TSSOP−8

(−40°C to +105°C)

NiPdAu

Tape & Reel,

3,000 Units / Reel

NV24C64C4UX4TG

WLCSP−4

with Die Coat

SnAgCu (SAC)

Tape & Reel,

5,000 Units / Reel

9. All packages are RoHS−compliant (Lead−free, Halogen−free).

10.The standard lead finish is NiPdAu.

11. Contact factory for availability.

12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

13.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultra violet light. When exposed to ultra violet light

the EEPROM cells lose their stored data.

ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

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PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NV24C64/D

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NV24C64DTUTG [ONSEMI]

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