NVMFD5873NL_14 [ONSEMI]
Power MOSFET;
| 型号： | NVMFD5873NL_14 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET |
| 文件： | 总6页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFD5873NL
Power MOSFET
60 V, 13 mW, 58 A, Dual N−Channel Logic
Level, Dual SO−8FL
Features
• Small Footprint (5x6 mm) for Compact Designs
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• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• NVMFD5873NLWF − Wettable Flanks Option for Enhanced Optical
Inspection
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
13 mW @ 10 V
60 V
58 A
16.5 mW @ 4.5 V
• AEC−Q101 Qualified and PPAP Capable
• This is a Pb−Free Device
Dual N−Channel
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
D1
D2
J
Parameter
Drain−to−Source Voltage
Symbol
Value
60
Unit
V
V
DSS
Gate−to−Source Voltage
V
"20
58
V
GS
G1
G2
Continuous Drain Cur-
T
= 25°C
I
A
mb
D
rent R
(Notes 1,
Y
J−mb
T = 100°C
mb
41
2, 3, 4)
Steady
State
S1
S2
Power Dissipation
T
mb
= 25°C
P
107
54
W
A
D
R
(Notes 1, 2, 3)
Y
J−mb
MARKING DIAGRAM
T
mb
= 100°C
D1 D1
Continuous Drain Cur-
T = 25°C
I
10
A
D
1
rent R
& 4)
(Notes 1, 3
S1
G1
S2
G2
D1
D1
D2
D2
q
JA
T = 100°C
A
7.0
Steady
State
DFN8 5x6
(SO8FL)
5873xx
AYWZZ
Power Dissipation
(Notes 1 & 3)
T = 25°C
P
3.1
1.6
190
W
A
D
CASE 506BT
R
q
JA
T = 100°C
A
D2 D2
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
5873NL = Specific Device Code
for NVMFD5873NL
5873LW = Specific Device Code
for NVMFD5873NLWF
Operating Junction and Storage Temperature
T , T
J
−55 to
175
°C
stg
Source Current (Body Diode)
I
58
40
A
S
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
Single Pulse Drain−to−Source Avalanche
E
mJ
AS
Energy (T = 25°C, V = 10 V, I = 28.3 A,
J
GS
L(pk)
L = 0.1 mH, R = 25 W)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
Package
Shipping
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
NVMFD5873NLT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
Parameter
Symbol
Value
Unit
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
R
1.4
Y
J−mb
NVMFD5873NLWFT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
°C/W
Junction−to−Ambient − Steady State (Note 3)
R
48
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second are higher but are dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 3
NVMFD5873NL/D
NVMFD5873NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
54.9
mV/°C
(BR)DSS
Zero Gate Voltage Drain Current
I
T = 25°C
1.0
100
100
mA
DSS
J
V
V
= 0 V,
GS
DS
= 60 V
= 0 V, V =
GS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
20 V
nA
GSS
DS
V
V
= V , I = 250 mA
1.5
2.5
V
GS(TH)
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.8
10.7
13.6
15
mV/°C
mW
GS(TH)
J
R
V
= 10 V, I = 15 A
13
DS(on)
GS
GS
DS
D
V
V
= 4.5 V, I = 10 A
16.5
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
= 5.0 V, I = 15 A
S
D
C
1560
145
98
pF
iss
Output Capacitance
C
oss
V
= 0 V, f = 1.0 MHz, V = 25 V
DS
GS
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
16.5
1.3
nC
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
G(TH)
V
= 4.5 V, V = 48 V,
DS
GS
I
D
= 15 A
Q
4.0
GS
GD
Q
8.8
Q
V
= 10 V, V = 48V, I = 15 A
30.5
nC
ns
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
10.8
51
d(on)
t
r
V
= 4.5 V, V = 48 V,
DS
GS
I
= 15 A, R = 2.5 W
D
G
Turn−Off Delay Time
Fall Time
t
t
t
21
d(off)
t
f
42.6
9.5
13
Turn−On Delay Time
Rise Time
ns
d(on)
t
r
V
V
= 10 V, V = 48 V,
DS
GS
I
D
= 15 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
25
d(off)
t
f
6.6
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
J
0.8
0.7
1.0
V
SD
= 0 V,
GS
S
I
= 15 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
22.4
14.5
9.0
ns
RR
t
t
a
V
GS
= 0 V, d /d = 100 A/ms,
IS t
I
S
= 15 A
Discharge Time
b
Reverse Recovery Charge
Q
18
nC
RR
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5873NL
TYPICAL CHARACTERISTICS
80
60
40
20
0
80
V
≥ 10 V
10 V
4.5 V
DS
3.8 V
3.4 V
60
40
20
0
T = 25°C
J
V
= 3.0 V
GS
T = 125°C
J
T = −55°C
J
T = 25°C
J
0.0
1.0
2.0
3.0
4.0
5.0
2.0
2.5
3.0
3.5
4.0
4.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.025
0.020
0.015
0.010
0.005
0.0200
0.0175
0.0150
0.0125
0.0100
0.0075
0.0050
T = 25°C
I
= 15 A
J
D
T = 25°C
J
V
= 4.5 V
GS
V
= 10 V
GS
2
3
4
5
6
7
8
9
10
5
10
15
20
25
30
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
100000
10000
1000
V
= 0 V
I
V
= 15 A
GS
D
= 10 V
GS
T = 150°C
J
T = 125°C
J
100
−50 −25
0
25
50
75
100 125 150 175
10
20
V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
30
40
50
60
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFD5873NL
TYPICAL CHARACTERISTICS
2000
1500
1000
500
0
10
V
= 0 V
Q
GS
T
C
iss
T = 25°C
J
8
6
4
2
0
Q
gs
Q
gd
T = 25°C
C
J
oss
V
DS
= 48 V
I
D
= 15 A
C
rss
0
10
20
30
40
50
60
0
5
10
15
20
25
30
35
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
80
70
60
50
40
30
20
10
0
1000
100
10
V
= 0 V
GS
V
= 48 V
= 15 A
= 10 V
DS
T = 25°C
J
I
D
V
GS
t
f
t
t
r
d(off)
t
d(on)
1
1
10
R , GATE RESISTANCE (W)
100
0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
0.01 ms
0.1 ms
1 ms
1
NVMFD5873NL
FBSOA
2
T = 25°C, 650 mm ,
A
10 ms
100
2 oz Cu Pad, V = 10 V
GS
0.1
0.1
1
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFD5873NL
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
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5
NVMFD5873NL
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1
4X
h
PIN ONE
IDENTIFIER
MILLIMETERS
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
2
3
4
−−−
TOP VIEW
D
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
D1
D2
D3
E
E1
E2
e
4.70
3.90
1.50
5.10
4.30
1.90
DETAIL B
0.10
0.10
C
ALTERNATE
DETAIL A
CONSTRUCTION
A
5.70
3.90
6.10
4.40
C
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
4.56
DETAIL A
G
h
0.45
−−−
0.65
2X
2.08
2X
0.56
−−−
12
−−−
−−−
_
8X
0.75
D2
D3
K
K1
L
M
N
0.51
0.56
0.48
3.25
1.80
−−−
−−−
0.61
3.50
0.71
3.75
2.20
4X L
K
e
2.00
1
4
4X
1.40
DETAIL B
6.59
4.84
2.30
3.70
4X
b1
N
E2
M
0.70
8
5
4X
G
b
8X
0.10
0.05
C
C
A B
K1
4X
1.27
PITCH
1.00
NOTE 3
BOTTOM VIEW
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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NVMFD5873NL/D
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