NVMFD5875NLT1G [ONSEMI]
Dual NâChannel Power MOSFET;
| 型号： | NVMFD5875NLT1G |
| 厂家： | 
ONSEMI |
| 描述： | Dual NâChannel Power MOSFET |
| 文件： | 总6页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFD5875NL
Product Preview
Power MOSFET
60 V, 33 mW, 22 A, Dual N−Channel, Logic
Level, Dual SO8FL
Features
• Low R
to Minimize Conduction Losses
DS(on)
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• Low Capacitance to Minimize Driver Losses
• NVMFD5875NLWF − Wettable Flanks Option for Enhanced Optical
Inspection
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
• AEC−Q101 Qualified and PPAP Capable
33 mW @ 10 V
45 mW @ 4.5 V
60 V
22 A
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
60
Unit
V
Dual N−Channel
V
DSS
D1
D2
Gate−to−Source Voltage
Continuous Drain Cur-
V
"20
22
V
GS
T
= 25°C
= 100°C
= 25°C
I
A
C
D
rent R
3, 4)
(Notes 1, 2,
q
JC
T
C
15
Steady
State
G1
G2
Power Dissipation
(Notes 1, 2, 3)
T
C
P
32
W
A
D
R
q
JC
S1
S2
T
C
= 100°C
16
Continuous Drain Cur-
T = 25°C
A
I
7
D
MARKING DIAGRAM
rent R
3, 4)
(Notes 1 &
q
JA
T = 100°C
A
5.8
3.2
2.2
80
Steady
State
D1 D1
S1
G1
S2
G2
D1
D1
D2
D2
Power Dissipation
(Notes 1, 3)
T = 25°C
A
P
W
D
1
R
q
JA
5875xx
AYWZZ
T = 100°C
A
DFN8 5x6
(SO8FL)
CASE 506BT
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
D2 D2
Operating Junction and Storage Temperature
T , T
−55 to
+175
°C
J
stg
5875NL = Specific Device Code
for NVMFD5875NL
Source Current (Body Diode)
I
S
19
A
5875LW = Specific Device Code
for NVMFD5875NLWF
Single Pulse Drain−
to−Source Avalanche
(I
= 14.5 A, L =
E
10.5
mJ
L(pk)
AS
0.1 mH)
A
Y
= Assembly Location
= Year
Energy (T = 25°C,
J
(I = 6.3 A, L =
40
V
DD
= 24 V, V
=
L(pk)
GS
W
ZZ
= Work Week
= Lot Traceability
2 mH)
10 V, R = 25 W)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
Package
Shipping
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
NVMFD5875NLT1G
NVMFD5875NLWFT1G
NVMFD5875NLT3G
NVMFD5875NLWFT3G
DFN8
(Pb−Free)
1500 / Tape &
Reel
Parameter
Symbol
Value
4.65
47
Unit
DFN8
(Pb−Free)
1500 / Tape &
Reel
Junction−to−Case − Steady State (Note 2, 3)
Junction−to−Ambient − Steady State (Note 3)
R
°C/W
q
JC
JA
R
q
DFN8
(Pb−Free)
5000 / Tape &
Reel
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
DFN8
(Pb−Free)
5000 / Tape &
Reel
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
November, 2015 − Rev. P1
NVMFD5875NL/D
NVMFD5875NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
53
mV/°C
(BR)DSS
T = 25°C
1.0
10
Zero Gate Voltage Drain Current
I
mA
J
DSS
V
V
= 0 V,
GS
DS
= 60 V
= 0 V, V =
GS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
20 V
100
nA
GSS
DS
V
V
= V , I = 250 mA
1.0
3.0
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
3.5
mV/°C
GS(TH)
J
V
= 10 V
= 4.5 V
I
I
= 7.5 A
= 7.5 A
27
37
33
45
Drain−to−Source On Resistance
R
mW
GS
D
DS(on)
V
GS
D
Forward Transconductance
g
FS
V
DS
= 15 V, I = 5.0 A
7.0
S
D
CHARGES AND CAPACITANCES
Input Capacitance
C
C
540
55
pF
nC
iss
Output Capacitance
V
GS
= 0 V, f = 1.0 MHz, V = 25 V
DS
oss
Reverse Transfer Capacitance
Total Gate Charge
C
36
rss
Q
5.9
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q
0.62
1.64
2.80
11
G(TH)
V
= 4.5 V, V = 48 V,
DS
GS
I
D
= 5.0 A
Q
GS
Q
GD
Q
V
= 10 V, V = 48V, I = 5.0A
20
nC
ns
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
t
8.1
15.8
11.8
3.9
d(on)
t
r
V
GS
= 4.5 V, V = 48 V,
DS
I
D
= 5.0 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
t
t
t
d(off)
t
f
Turn−On Delay Time
Rise Time
4.9
ns
d(on)
t
r
6.4
V
= 10 V, V = 48 V,
DS
GS
I
D
= 5.0 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
14.5
2.4
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
T = 25°C
0.8
0.7
1.2
Forward Diode Voltage
V
SD
V
J
V
= 0 V,
= 5.0 A
GS
I
S
T = 125°C
J
Reverse Recovery Time
Charge Time
t
14.5
11.5
3.1
ns
RR
t
t
a
V
GS
= 0 V, d /d = 100 A/ms,
IS t
I
S
= 5.0 A
Discharge Time
b
Reverse Recovery Charge
Q
11
nC
nH
RR
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance
L
0.93
0.005
1.84
1.5
S
D
G
L
T = 25°C
A
Gate Inductance
L
Gate Resistance
R
W
G
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5875NL
TYPICAL CHARACTERISTICS
30
40
36
32
28
24
20
16
12
8
5 V
T = 25°C
V
GS
= 10 V
J
V
DS
≥ 10 V
4.5 V
20
10
0
4.0 V
T = 25°C
J
3.5 V
3.0 V
4
T = 125°C
J
T = −55°C
J
0
0
1
2
3
4
5
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
T = 25°C
I
= 10 A
J
D
T = 25°C
J
V
V
= 4.5 V
= 10 V
GS
GS
3
4
5
6
7
8
9
10
5
8
11
14
17
20
23
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−10
1E−11
1E−12
V
GS
= 0 V
I
V
= 7.5 A
D
= 10 V
GS
T = 150°C
J
T = 125°C
J
T = 25°C
J
5
10 15 20 25 30 35 40 45 50 55 60
, DRAIN−TO−SOURCE VOLTAGE (V)
−50 −25
0
25
50
75
100 125 150 175
T , JUNCTION TEMPERATURE (°C)
J
V
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFD5875NL
TYPICAL CHARACTERISTICS
10
800
700
600
500
400
300
200
100
0
Q
T
V
= 0 V
GS
9
8
7
6
5
4
3
2
1
0
T = 25°C
J
C
iss
Q
Q
gs
gd
T = 25°C
J
V
DD
= 48 V
C
oss
I
D
= 5 A
C
rss
0
5
10
15
20
25
30
0
1
2
3
4
5
6
7
8
9
10 11
DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Gate Charge
1000
100
10
40
30
20
V
= 48 V
= 5 A
= 10 V
DD
V
= 0 V
GS
I
D
T = 25°C
J
V
GS
t
t
d(off)
t
f
t
r
d(on)
10
0
1
1
10
R , GATE RESISTANCE (W)
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage
100
10 ms
100 ms
10
1 ms
V
= 20 V
GS
10 ms
Single Pulse
= 25°C
1
T
C
R
Limit
dc
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
V
DS
, DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFD5875NL
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
1
0.01
2
Device Mounted on 650 mm
2 oz Cu PCB
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
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5
NVMFD5875NL
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1
4X
h
PIN ONE
IDENTIFIER
MILLIMETERS
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
2
3
4
−−−
TOP VIEW
D
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
DETAIL B
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
ALTERNATE
CONSTRUCTION
DETAIL A
A
5.70
3.90
6.10
4.40
C
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
4.56
DETAIL A
0.45
−−−
0.65
2X
2.08
2X
0.56
12
−−−
−−−
_
8X
0.75
D2
D3
0.51
0.56
0.48
3.25
1.80
−−−
0.61
3.50
2.00
0.71
3.75
2.20
4X L
K
M
N
e
1
4
4X
1.40
DETAIL B
6.59
4.84
2.30
4X
b1
3.70
N
E2
M
0.70
8
5
4X
G
b
8X
0.10
0.05
C
C
A B
K1
4X
1.27
PITCH
1.00
NOTE 3
BOTTOM VIEW
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NVMFD5875NL/D
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