NVMFD5C446NLWFT1G [ONSEMI]
双 N 沟道，功率 MOSFET，40V，145A，2.65mΩ;
| 型号： | NVMFD5C446NLWFT1G |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，功率 MOSFET，40V，145A，2.65mΩ |
| 文件： | 总7页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMFD5C446NL
MOSFET – Power, Dual
N-Channel
40 V, 2.65 mW, 145 A
Features
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• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• NVMFD5C446NLWF − Wettable Flank Option for Enhanced Optical
Inspection
2.65 mꢂ @ 10 V
3.9 mꢂ @ 4.5 V
40 V
145 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Dual N−Channel
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D1
D2
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
G1
G2
Continuous Drain
Current R
T
= 25°C
I
145
A
C
D
ꢀ
JC
T
C
= 100°C
105
(Notes 1, 2, 3)
Steady
State
S1
S2
Power Dissipation
T
C
= 25°C
P
125
62
W
A
D
R
(Notes 1, 2)
ꢀ
JC
T
C
= 100°C
MARKING
DIAGRAM
Continuous Drain
Current R
T = 25°C
A
I
D
25
ꢀ
JA
T = 100°C
A
18
(Notes 1, 2, 3)
Steady
State
D1 D1
Power Dissipation
T = 25°C
A
P
3.5
1.8
644
W
S1
G1
S2
G2
D1
D
1
R
(Notes 1 & 2)
D1
D2
D2
ꢀ
JA
XXXXXX
AYWZZ
T = 100°C
A
DFN8 5x6
(SO8FL)
Pulsed Drain Current
T = 25°C, t = 10 ꢁ s
I
DM
A
A
p
CASE 506BT
D2 D2
Operating Junction and Storage Temperature
T , T
−55 to
+ 175
°C
J
stg
A
Y
= Assembly Location
= Year
Source Current (Body Diode)
I
91
A
S
W
ZZ
= Work Week
= Lot Traceability
Single Pulse Drain−to−Source Avalanche
E
AS
171
mJ
Energy (T = 25°C, I
= 11 A)
J
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
R
1.38
46.9
°C/W
ꢀ
JC
Junction−to−Ambient − Steady State (Note 2)
R
ꢀ
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
July. 2019 − Rev. 0
NVMFD5C446NL/D
NVMFD5C446NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 ꢁ A
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
23
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
10
DSS
GS
DS
J
V
= 40 V
ꢁ
A
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 90 ꢁ A
1.2
2.2
V
GS(TH)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.2
2.2
mV/°C
GS(TH)
J
R
V
= 10 V
I
I
= 20 A
= 20 A
2.65
3.9
DS(on)
GS
D
mꢂ
V
GS
= 4.5 V
3.0
D
Forward Transconductance
g
FS
V
DS
= 15 V, I = 50 A
138
S
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
3170
1270
48
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 25 V
pF
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
Q
V
GS
= 4.5 V, V = 32 V; I = 50 A
25
G(TOT)
G(TOT)
DS
D
Total Gate Charge
V
GS
= 10 V, V = 32 V; I = 50 A
54
DS
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
5.7
nC
V
G(TH)
Q
10.7
7.0
GS
GD
GP
V
GS
= 4.5 V, V = 32 V; I = 50 A
DS D
Q
V
5.7
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
14.8
16.8
34.9
15.2
d(ON)
Rise Time
t
r
V
= 4.5 V, V = 32 V,
DS
GS
D
ns
V
I
= 5 A, R = 1.0 ꢂ
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.8
0.7
54
24
30
55
1.2
SD
J
V
S
= 0 V,
GS
I
= 20 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
a
V
GS
= 0 V, dIS/dt = 50 A/ꢁ s,
I
S
= 5 A
Discharge Time
t
b
Reverse Recovery Charge
Q
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ꢁ s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5C446NL
TYPICAL CHARACTERISTICS
220
200
180
160
140
120
100
80
180
10 to 5 V
4.5 V
V
DS
= 10 V
160
140
120
100
80
3.8 V
3.6 V
3.4 V
V
GS
= 3.2 V
60
60
T = 25°C
J
40
40
20
0
20
0
T = 125°C
T = −55°C
J
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
4.0
3.5
3.0
2.5
6
5
4
3
2
I
= 20 A
D
T = 25°C
J
T = 25°C
J
V
= 4.5 V
= 10 V
GS
V
GS
2.0
1.5
1
0
3
4
5
6
7
8
9
10
15
25
35
45
55
65
75
85
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1M
2.1
1.9
1.7
I
V
= 20 A
D
T = 175°C
J
100K
10K
1K
= 10 V
GS
T = 150°C
J
T = 125°C
J
1.5
1.3
1.1
0.9
T = 85°C
J
100
10
T = 25°C
J
1
0.7
0.5
−50 −25
0.1
0
25
50
75 100 125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD5C446NL
TYPICAL CHARACTERISTICS
10
10K
1K
V
DS
= 32 V
9
8
7
6
5
4
3
2
C
C
iss
I
D
= 50 A
T = 25°C
J
oss
Q
Q
GS
GD
100
10
T = 25°C
GS
f = 1 MHz
J
V
C
rss
= 0 V
1
0
0
5
10
15
20
25
30
35
40
0
10
20
30
40
50
Q , TOTAL GATE CHARGE (nC)
G
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
1000
V
GS
= 0 V
V
V
= 4.5 V
= 32 V
GS
DS
I
D
= 5 A
t
d(off)
t
t
f
10
r
100
10
t
d(on)
T = 125°C
J
T = 25°C
J
T = −55°C
J
1
1
10
R , GATE RESISTANCE (ꢂ)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
T
= 25°C
J(initial)
T
V
= 25°C
C
10
10
T
= 100°C
J(initial)
≤ 10 V
GS
10 ꢁ s
Single Pulse
1
0.5 ms
1 ms
10 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD5C446NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.000001 0.00001
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD5C446NLT1G
5C446L
DFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFD5C446NLWFT1G
446LWF
DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
DATE 23 NOV 2021
2X
SCALE 2:1
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
E1
MILLIMETERS
IDENTIFIER
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
NOM
−−−
−−−
0.42
0.42
−−−
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
4X
h
1
2
3
4
c
TOP VIEW
D
A1
D1
D2
D3
E
E1
E2
e
G
h
K
K1
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
A
DETAIL B
5.70
3.90
6.10
4.40
ALTERNATE
SEATING
PLANE
NOTE 6
DETAIL A
CONSTRUCTION
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
L
M
N
0.71
3.75
2.20
4X L
K
3.50
2.00
e
1
4
SOLDERING FOOTPRINT*
DETAIL B
4.56
4X
2X
2.08
2X
0.56
b1
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
NOTE 3
2.30
BOTTOM VIEW
3.70
GENERIC
MARKING DIAGRAM*
0.70
1
XXXXXX
AYWZZ
4X
1.27
PITCH
1.00
5.55
XXXXXX = Specific Device Code
DIMENSION: MILLIMETERS
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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