NVMFD6H846NL [ONSEMI]
MOSFET - Power, Dual N-Channel;
| 型号： | NVMFD6H846NL |
| 厂家： | 
ONSEMI |
| 描述： | MOSFET - Power, Dual N-Channel |
| 文件： | 总7页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET - Power, Dual
N-Channel
80 V, 15 mW, 31 A
NVMFD6H846NL
Features
www.onsemi.com
• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• NVMFD6H846NLWF − Wettable Flank Option for Enhanced
Optical Inspection
15 mW @ 10 V
19 mW @ 4.5 V
80 V
31 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Dual N−Channel
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D1
D2
Parameter
Drain−to−Source Voltage
Symbol
Value
80
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
31
A
G1
G2
C
D
q
JC
T
C
22
(Notes 1, 2, 3)
Steady
State
S1
S2
Power Dissipation
T
C
P
34
W
A
D
R
(Notes 1, 2)
q
JC
T
C
= 100°C
17
Continuous Drain
Current R
T = 25°C
A
I
D
9.4
6.7
3.2
1.6
114
MARKING
DIAGRAM
q
JA
T = 100°C
A
(Notes 1, 2, 3)
Steady
State
D1 D1
Power Dissipation
T = 25°C
A
P
W
D
S1
G1
S2
G2
D1
1
R
(Notes 1, 2)
q
JA
D1
D2
D2
XXXXXX
AYWZZ
T = 100°C
A
DFN8 5x6
(SO8FL)
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
CASE 506BT
D2 D2
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
A
Y
= Assembly Location
= Year
Source Current (Body Diode)
I
28
A
S
W
ZZ
= Work Week
= Lot Traceability
Single Pulse Drain−to−Source Avalanche
E
AS
201
mJ
Energy (T = 25°C, I
= 1.1 A)
J
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
4.4
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
47
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
March, 2020 − Rev. 0
NVMFD6H846NL/D
NVMFD6H846NL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
80
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
47.1
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
10
DSS
GS
DS
J
V
= 80 V
mA
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 21 mA
1.2
2.0
V
GS(TH)
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
−5.5
12.2
15.1
50
mV/°C
GS(TH)
J
R
V
= 10 V
I
I
= 5 A
= 5 A
15
19
DS(on)
GS
D
mW
V
GS
= 4.5 V
D
Forward Transconductance
g
FS
V
= 8 V, I = 15 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
900
120
7
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 40 V
pF
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
Q
V
GS
= 10 V, V = 40 V; I = 15 A
17
8
G(TOT)
G(TOT)
DS
D
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
2
nC
V
G(TH)
Q
3
V
GS
= 4.5 V, V = 40 V; I = 15 A
GS
GD
GP
DS
D
Q
V
3
3.2
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
10
40
20
7
d(ON)
Rise Time
t
r
V
= 4.5 V, V = 64 V,
DS
GS
D
ns
V
I
= 15 A, R = 2.5 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.79
0.64
32
1.2
SD
RR
J
V
= 0 V,
GS
S
I
= 5 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
t
20
ns
a
V
= 0 V, dIS/dt = 100 A/ms,
GS
I
S
= 15 A
Discharge Time
t
12
b
Reverse Recovery Charge
Q
25
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
www.onsemi.com
2
NVMFD6H846NL
TYPICAL CHARACTERISTICS
30
25
20
15
10
14
3.2 V
V
= 10 V to 3.6 V
GS
12
3.4 V
3.0 V
10
8
6
2.8 V
2.6 V
T = 25°C
J
4
5
0
2
0
T = 125°C
J
T = −55°C
J
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
25
20
15
10
18
17
16
15
14
13
12
T = 25°C
D
T = 25°C
J
J
I
= 5 A
V
= 4.5 V
= 10 V
4
GS
V
GS
5
0
11
10
3
4
5
6
7
8
9
10
1
2
3
5
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
100
10
2.5
2.0
1.5
T = 175°C
J
V
= 10 V
= 5 A
GS
I
D
T = 150°C
J
T = 125°C
J
1
T = 85°C
J
0.1
0.01
1.0
0.5
T = 25°C
J
0.001
0.0001
−50 −25
0
25
50
75 100 125 150 175
5
15
25
35
45
55
65
75
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD6H846NL
TYPICAL CHARACTERISTICS
10K
1K
10
9
8
7
6
5
4
3
2
C
ISS
C
OSS
100
Q
Q
4
GS
GD
10
1
V
DS
= 40 V
C
V
= 0 V
RSS
GS
I
D
= 15 A
T = 25°C
J
1
0
T = 25°C
J
f = 1 MHz
0
10
20
30
40
50
60
70
80
0
2
6
8
10
12
14
16
18
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
5
V
GS
= 0 V
t
r
t
t
d(off)
d(on)
10
t
f
V
V
= 4.5 V
= 64 V
GS
DS
I
D
= 15 A
T = −55°C
J
T = 125°C
J
T = 25°C
J
1
1
1
10
R , GATE RESISTANCE (W)
50
0.3
0.4
0.5
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.6
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
10
T = 25°C
A
Single Pulse
V
GS
≤ 10 V
T
= 25°C
J(initial)
0.5 ms
10 ms
10
T
= 100°C
1
J(initial)
1
R
Limit
DS(on)
1 ms
Thermal Limit
Package Limit
10 ms
0.1
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD6H846NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD6H846NLT1G
6H846L
DFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFD6H846NLWFT1G
846LWF
DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
1
DATE 26 FEB 2013
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
IDENTIFIER
E1
4X
h
MILLIMETERS
GENERIC
MARKING DIAGRAM*
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
1
2
3
4
XXXXXX
AYWZZ
−−−
TOP VIEW
5.15 BSC
4.90
4.10
1.70
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
DETAIL A
A
6.15 BSC
5.90
4.15
XXXXXX= Specific Device Code
5.70
3.90
6.10
4.40
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
1.27 BSC
0.55
DETAIL A
0.45
−−−
0.65
−−−
12
−−−
−−−
_
D2
D3
0.51
0.56
0.48
3.25
1.80
−−−
−−−
0.61
3.50
*This information is generic. Please refer
to device data sheet for actual part
marking.
0.71
3.75
2.20
4X L
K
e
2.00
1
4
DETAIL B
ALTERNATE
DETAIL B
CONSTRUCTION
4X
b1
N
SOLDERING FOOTPRINT*
E2
M
4.56
2X
2.08
2X
0.56
8X
0.75
8
5
4X
G
b
8X
0.10
0.05
C
C
A B
K1
NOTE 3
BOTTOM VIEW
4X
1.40
6.59
4.84
2.30
3.70
0.70
4X
1.27
PITCH
1.00
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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www.onsemi.com
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