NVMFS4C308NT1G [ONSEMI]
Power MOSFET 30V, 55A, 4.8 mΩ, Single N-Channel, SO8-FL, Logic Level.;
| 型号： | NVMFS4C308NT1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 30V, 55A, 4.8 mΩ, Single N-Channel, SO8-FL, Logic Level. |
| 文件： | 总9页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET - Power, Single
N-Channel, DFN5/DFNW5
30 V, 4.8 mW, 55 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
4.8 mW @ 10 V
7.0 mW @ 4.5 V
30 V
55 A
NVMFS4C308N
D (5−8)
Features
• Low R
to Minimize Conduction Losses
DS(on)
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• AEC−Q101 Qualified and PPAP Capable
G (4)
S (1,2,3)
N−CHANNEL MOSFET
• NVMFS4C308NWF − Wettable Flanks Option for Enhanced Optical
Inspection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
MARKING
DIAGRAM
D
Compliant
DFN5
CASE 488AA
Applications
1
• Reverse Battery Protection
• DC−DC Converters Output Driver
S
S
S
G
D
D
XXXXXX
AYWZZ
DFNW5
CASE 507BA
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
D
4C08N = Specific Device Code for
NVMFS4C308N
4C08WF= Specific Device Code of
NVMFS4C308NWF
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
30
Unit
V
V
DSS
V
GS
20
V
A
Y
= Assembly Location
= Year
Continuous Drain
Current R
T = 25°C
17.2
12.3
3
A
A
I
D
q
JA
W
ZZ
= Work Week
= Lot Traceabililty
T = 100°C
A
(Notes 1, 2)
Power Dissipation
T = 25°C
A
W
P
D
R
(Notes 1, 2)
q
JA
ORDERING INFORMATION
Continuous Drain
Current R
T
= 25°C
55
39
C
Steady
State
q
JC
†
Device
Package
Shipping
(Notes 1, 2, 3)
I
D
A
NVMFS4C308NT1G
DFN5
1500 /
Continuous Drain
Current R
T = 100°C
C
(Pb−Free) Tape & Reel
q
JC
(Notes 1, 2, 3)
NVMFS4C308NWFT1G DFNW5 1500 /
Power Dissipation
T
= 25°C
P
30.6
144
W
(Pb−Free) Tape & Reel
C
D
R
(Notes 1, 2, 3)
q
JC
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature T , T
Range
−55 to
+175
°C
J
STG
Source Current (Body Diode)
I
23
42
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (T = 25°C, V = 10 V, I = 29 A ,
J
GS
L
pk
L = 0.1 mH, R = 25 W) (Note 3)
GS
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
3. This is the absolute maximum rating. Parts are 100% tested at T = 25°C,
J
V
GS
= 10 V, I = 21 Apk, E = 22 mJ.
L AS
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
September, 2021 − Rev. 1
NVMFS4C308N/D
NVMFS4C308N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
4.9
Unit
Junction−to−Case (Drain)
R
q
JC
°C/W
Junction−to−Ambient – Steady State
R
49.8
q
JA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
= 0 V, I = 250 mA
30
34
V
V
(BR)DSS
GS
D
Drain−to−Source Breakdown Voltage
(transient)
V
V
= 0 V, I
= 8.4 A,
= 100 ns
(BR)DSSt
GS
case
D(aval)
T
= 25°C, t
transient
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
13.8
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
= 24 V
T = 25°C
1.0
10
DSS
GS
DS
J
V
mA
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V
=
20 V
100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.3
0.3
2.1
V
GS(TH)
GS
DS
D
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
J
4.9
4.0
5.9
42
mV/°C
GS(TH)
R
V
GS
= 10 V
I
I
= 30 A
= 30 A
4.8
7.0
DS(on)
D
mW
V
GS
= 4.5 V
D
Forward Transconductance
Gate Resistance
g
FS
V
= 1.5 V, I = 15 A
S
DS
D
R
T = 25°C
A
1.0
2.0
W
G
CHARGES AND CAPACITANCES
Input Capacitance
C
1113
702
39
1670
ISS
Output Capacitance
Reverse Transfer Capacitance
Capacitance Ratio
C
V
= 0 V, f = 1 MHz, V = 15 V
pF
nC
OSS
RSS
GS
DS
C
C
/C
V
GS
= 0 V, V = 15 V, f = 1 MHz
0.035
8.4
RSS ISS
DS
Total Gate Charge
Q
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Gate Plateau Voltage
Total Gate Charge
Q
1.8
G(TH)
Q
3.5
V
= 4.5 V, V = 15 V; I = 30 A
GS
GD
GP
GS
DS
D
Q
V
3.3
3.4
V
Q
V
= 10 V, V = 15 V; I = 30 A
18.2
nC
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
t
9.0
33
d(ON)
t
r
V
= 4.5 V, V = 15 V,
DS
GS
D
ns
ns
I
= 15 A, R = 3.0 W
G
Turn−Off Delay Time
Fall Time
t
15
d(OFF)
t
f
4.0
7.0
26
Turn−On Delay Time
Rise Time
t
d(ON)
t
r
V
= 10 V, V = 15 V,
DS
GS
I
D
= 15 A, R = 3.0 W
G
Turn−Off Delay Time
Fall Time
t
19
d(OFF)
t
f
3.0
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS4C308N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.79
0.66
28.3
14.5
13.8
15.3
1.1
SD
J
V
S
= 0 V,
GS
V
I
= 10 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
a
V
= 0 V, dIS/dt = 100 A/ms,
GS
I
S
= 30 A
Discharge Time
t
b
Reverse Recovery Charge
Q
nC
RR
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
NVMFS4C308N
TYPICAL CHARACTERISTICS
80
100
90
80
70
60
50
4.5 V to 10 V
V
= 3 V
DS
4.2 V
4.0 V
70
60
50
40
30
20
T = 25°C
J
3.8 V
3.6 V
3.4 V
40
30
20
T = 125°C
J
3.2 V
T = 25°C
J
3.0 V
2.8 V
10
0
10
0
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
, GATE−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.010
0.009
0.008
0.007
0.006
0.005
0.004
I
D
= 30 A
T = 25°C
J
V
= 4.5 V
GS
V
= 10 V
GS
0.003
0.002
0.004
0.002
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
10
20
30
40
50
60
70
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
1000
2.0
1.5
V
GS
= 0 V
T = 150°C
V
= 10 V
= 18 A
J
GS
I
D
T = 125°C
J
T = 85°C
J
100
10
1.0
0.5
−50 −25
0
25
50
75 100 125 150 175
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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4
NVMFS4C308N
TYPICAL CHARACTERISTICS
10
1800
1600
1400
1200
1000
800
Q
T
V
= 0 V
GS
T = 25°C
J
8
6
4
C
C
iss
Q
Q
oss
gd
gs
600
T = 25°C
J
V
V
= 15 V
= 10 V
= 30 A
DD
400
2
0
GS
200
0
I
D
C
rss
0
5
10
15
20
25
30
0
2
4
6
8
10 12 14 16 18 20
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
20
18
16
14
12
10
8
1000
100
V
= 15 V
= 15 A
= 10 V
DD
V
= 0 V
GS
I
D
V
GS
t
t
r
f
t
d(off)
t
d(on)
10
1
6
T = 125°C
J
4
T = 25°C
J
2
0
1
10
R , GATE RESISTANCE (W)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
, SOURCE−TO−DRAIN VOLTAGE (V)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
10 ms
100 ms
1 ms
10 ms
0 V < V < 10 V
Single Pulse
GS
1
T
C
= 25°C
0.1
R
Limit
dc
DS(on)
Thermal Limit
Package Limit
0.01
0.01
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
NVMFS4C308N
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 50%
20%
10%
5%
2%
1%
1
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
100
80
70
60
50
40
30
20
T = 25°C
A
T = 85°C
A
10
10
0
1
1.E−08 1.E−07
0
10
20
30
40
(A)
50
60
70
1.E−06
1.E−05
1.E−04 1.E−03
I
D
PULSE WIDTH (SECONDS)
Figure 13. GFS vs. ID
Figure 14. Avalanche Characteristics
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1. ANODE
2. ANODE
2X
0.905
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
DIMENSIONS: MILLIMETERS
4X
0.750
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW5 5x6 (FULL−CUT SO8FL WF)
CASE 507BA
ISSUE A
DATE 03 FEB 2021
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
A
Y
= Assembly Location
= Year
W
ZZ
= Work Week
= Lot Traceability
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26450H
DFNW5 5x6 (FULL−CUT SO8FL WF)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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