NVMFWD020N06CT1G [ONSEMI]
Power MOSFET Power, N-Channel, DUAL SO8FL, 60 V, 16.3 mΩ, 32 A;
| 型号： | NVMFWD020N06CT1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET Power, N-Channel, DUAL SO8FL, 60 V, 16.3 mΩ, 32 A |
| 文件： | 总7页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET - Power, Dual
N-Channel, DUAL SO8FL
60 V, 20.3 mW, 27 A
NVMFD020N06C
Features
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• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• NVMFWD020N06C − Wettable Flank Option for Enhanced Optical
Inspection
60 V
20.3 mW @ 10 V
27 A
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol Value Units
V
60
20
27
19
31
15
8
V
V
A
DSS
V
GS
Continuous Drain
Current R
Steady
State
T
= 25°C
= 100°C
= 25°C
I
D
C
q
JC
T
C
(Notes 1, 3)
MARKING
DIAGRAM
Power Dissipation
Steady
State
T
C
P
W
A
D
R
(Note 1)
q
JC
T
C
= 100°C
1
Continuous Drain
Current R
Steady
State
T = 25°C
A
I
D
XXXXXX
AYWZZ
DFN8 5x6
(SO8FL)
q
JA
T = 100°C
A
6
(Notes 1, 2, 3)
CASE 506BT
Power Dissipation
Steady
State
T = 25°C
P
3.1
1.5
98
W
A
D
R
(Notes 1, 2)
q
JA
T = 100°C
A
XXXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
Pulsed Drain Current T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
W
ZZ
= Work Week
= Lot Traceability
J
stg
Source Current (Body Diode)
I
25
16
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I = 5.7 A
)
L
pk
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
Lead Temperature Soldering Reflow for
Soldering Purposes (1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
March, 2020 − Rev. 1
NVMFD020N06C/D
NVMFD020N06C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
4.8
47
Unit
Junction−to−Case – Steady State (Note 2)
Junction−to−Ambient – Steady State (Note 2)
R
q
JC
°C/W
R
q
JA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
I
D
= 250 mA, ref to 25°C
29
mV/°C
(BR)DSS
/ T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25°C
10
mA
DSS
GS
DS
J
V
= 60 V
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
DS
= 0 V, V = 20 V
nA
GSS
GS
V
V
GS
= V , I = 20 mA
2.0
4.0
V
GS(TH)
DS
D
Negative Threshold Temperature
Coefficient
V
/ T
J
I = 20 mA, ref to 25°C
D
−7.8
mV/°C
GS(TH)
Drain−to−Source On Resistance
Forward Transconductance
Gate Resistance
R
V
= 10 V, I = 4 A
16.9
12
20.3
mW
S
DS(on)
GS
D
g
FS
V
= 5 V, I = 4 A
DS D
R
T = 25°C
A
1.0
W
G
CHARGES & CAPACITANCES
Input Capacitance
C
355
260
4.9
pF
nC
ISS
Output Capacitance
C
V
GS
= 0 V, f = 1 MHz, V = 30 V
DS
OSS
RSS
Reverse Capacitance
Total Gate Charge
C
Q
5.8
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
1.4
G(TH)
V
GS
= 10 V, V = 48 V, I = 4 A
DS D
Q
2.3
GS
Q
0.53
GD
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
t
6.5
1.4
9.7
4.0
ns
d(ON)
t
r
V
GS
I
= 10 V, V = 48 V,
DS
= 4 A, R = 6 W
D
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
T = 25°C
0.81
0.67
24
1.2
V
J
V
= 0 V,
= 4 A
GS
S
Forward Voltage
V
SD
I
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
ta
12
V
= 0 V, d /d = 100 A/ms,
IS t
GS
V
= 30 V, I = 4 A
DS
S
Discharge Time
tb
12
Reverse Recovery Charge
Q
12
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
2
NVMFD020N06C
TYPICAL CHARACTERISTICS
70
60
50
40
30
20
35
V
GS
= 10 V to 7.0 V
30
25
20
15
10
6.0 V
5.0 V
4.5 V
3.6 V
T = −55°C
J
T = 25°C
J
10
0
5
0
T = 125°C
J
0
1
2
3
4
5
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
22
21
20
19
18
20
19
18
T = 25°C
J
T = 25°C
D
J
I
= 4 A
V
GS
= 10 V
17
16
15
17
16
7.0
7.5
8.0
8.5
9.0
9.5
10
4
8
12
16
20
24
26
32
V
GS
, GATE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1.8
100K
10K
1K
V
I
= 10 V
= 4 A
GS
T = 175°C
J
D
1.6
1.4
1.2
1.0
0.8
T = 150°C
J
T = 125°C
J
100
10
T = 85°C
J
T = 25°C
1
J
0.6
0.4
0.1
−50
−25
0
25
50
75
100
125
150
5
15
25
35
45
55
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD020N06C
TYPICAL CHARACTERISTICS
10K
1K
10
V
= 48 V
= 4 A
DS
9
8
7
6
5
4
3
2
I
D
T = 25°C
J
C
C
ISS
Q
GD
Q
OSS
GS
100
10
1
V
= 0 V
GS
C
RSS
T = 25°C
J
1
0
f = 1 MHz
0
1
1
10
20
30
40
50
60
0
1
2
3
4
5
6
7
V
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
DS
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
10
10
V
V
= 10 V
= 48 V
= 4 A
GS
V
= 0 V
GS
DS
I
D
t
d(off)
t
d(on)
1
t
f
1
t
r
T = 125°C
T = 25°C
T = −55°C
J
J
J
0.1
0.1
10
R , GATE RESISTANCE (W)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
T
= 25°C
Single Pulse
≤ 10 V
C
V
100
10
GS
10 ms
100 ms
1 ms
T
= 25°C
J(initial)
10
T
= 100°C
1
J(initial)
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
100
100 ms & 1 S
1
0.1
10
, DRAIN−SOURCE VOLTAGE(V)
0.000001
0.00001
0.0001
0.001
0.01
V
T , TIME IN AVALANCHE (s)
AV
DS
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMFD020N06C
TYPICAL CHARACTERISTICS
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.000001
0.01
0.00001
0.0001
0.001
PULSE TIME (sec)
0.01
0.1
1
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD020N06CT1G
20DN6C
SO8FL Dual
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFWD020N06CT1G
20DN6W
SO8FL Dual
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
DATE 23 NOV 2021
2X
SCALE 2:1
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
E1
MILLIMETERS
IDENTIFIER
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
NOM
−−−
−−−
0.42
0.42
−−−
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
4X
h
1
2
3
4
c
TOP VIEW
D
A1
D1
D2
D3
E
E1
E2
e
G
h
K
K1
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
A
DETAIL B
5.70
3.90
6.10
4.40
ALTERNATE
SEATING
PLANE
NOTE 6
DETAIL A
CONSTRUCTION
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
L
M
N
0.71
3.75
2.20
4X L
K
3.50
2.00
e
1
4
SOLDERING FOOTPRINT*
DETAIL B
4.56
4X
2X
2.08
2X
0.56
b1
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
NOTE 3
2.30
BOTTOM VIEW
3.70
GENERIC
MARKING DIAGRAM*
0.70
1
XXXXXX
AYWZZ
4X
1.27
PITCH
1.00
5.55
XXXXXX = Specific Device Code
DIMENSION: MILLIMETERS
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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