NVMJS1D2N04CLTWG [ONSEMI]
Power MOSFET 40 V, 1.2mΩ, 237 A, Single N-Channel;
| 型号： | NVMJS1D2N04CLTWG |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 40 V, 1.2mΩ, 237 A, Single N-Channel |
| 文件： | 总7页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVMJS1D2N04CL
MOSFET – Power, Single
N-Channel
40 V, 1.2 mW, 237 A
Features
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• Small Footprint (5x6 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• LFPAK8 Package, Industry Standard
1.2 mW @ 10 V
1.8 mW @ 4.5 V
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
40 V
237 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D (5,8)
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
G (4)
Continuous Drain
Current R
Steady
State
T
= 25°C
= 100°C
= 25°C
I
237
168
128
64
A
C
D
q
JC
T
C
(Notes 1, 3)
S (1,2,3)
N−CHANNEL MOSFET
Power Dissipation
T
C
P
W
A
D
R
(Note 1)
q
JC
T
C
= 100°C
Continuous Drain
Current R
Steady
State
T = 25°C
A
I
D
41
MARKING
DIAGRAM
q
JA
T = 100°C
A
29
(Notes 1, 2, 3)
Power Dissipation
T = 25°C
P
3.8
1.9
1480
W
A
D
D
D
D
D
R
(Notes 1, 2)
q
JA
T = 100°C
A
1D2N04
CL
AWLYW
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature
Range
T , T
J
−55 to
+ 175
°C
stg
LFPAK8
CASE 760AA
Source Current (Body Diode)
I
107
453
A
S
1
S
S
S
G
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I
= 19 A)
1D2N04CL = Specific Device Code
L(pk)
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
W
= Work Week
THERMAL RESISTANCE MAXIMUM RATINGS
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
Parameter
Symbol
Value
1.2
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
36
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
July, 2019 − Rev. 0
NVMJS1D2N04CL/D
NVMJS1D2N04CL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
20
mV/°C
(BR)DSS
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25°C
10
mA
DSS
GS
DS
J
V
= 40 V
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
V
V
= V , I = 170 mA
1.2
2.0
V
mV/°C
mW
mW
S
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
Drain−to−Source On Resistance
Forward Transconductance
V
/T
J
−5.9
1.5
GS(TH)
R
R
V
GS
= 4.5 V
= 10 V
I
I
= 50 A
= 50 A
1.8
1.2
DS(on)
DS(on)
D
V
GS
1.0
D
g
FS
V
= 10 V, I = 50 A
190
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
V
= 0 V, f = 1 MHz, V = 25 V
5600
2600
70
pF
ISS
GS
DS
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
Total Gate Charge
C
Q
Q
V
GS
= 4.5 V, V = 32 V; I = 50 A
44
nC
nC
G(TOT)
G(TOT)
DS
D
Total Gate Charge
V
V
= 10 V, V = 32 V; I = 50 A
93
GS
DS
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
= 10 V, V = 32 V; I = 50 A
9.4
G(TH)
GS
DS
D
Q
17.2
13.6
3.1
GS
GD
GP
Q
V
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
V
= 10 V, V = 32 V,
24
72
ns
d(ON)
GS
D
DS
I
= 50 A, R = 2.5 W
G
Rise Time
t
r
Turn−Off Delay Time
t
122
116
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
S
= 0 V,
T = 25°C
0.76
0.66
59
1.2
V
SD
GS
J
I
= 50 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
V
= 0 V, dIS/dt = 100 A/ms,
ns
RR
GS
I
S
= 50 A
t
t
29
a
Discharge Time
30
b
Reverse Recovery Charge
Q
43
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMJS1D2N04CL
TYPICAL CHARACTERISTICS
200
180
160
140
120
100
80
250
V
GS
= 10 V to 3.6 V
V
DS
= 10 V
3.4 V
3.2 V
200
150
100
3.0 V
2.8 V
T = 25°C
J
60
40
50
0
20
0
T = 125°C
J
T = −55°C
J
0
1
2
3
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
10
9
2.0
1.5
1.0
T = 25°C
J
8
7
6
5
4
3
0.5
0
2
1
0
2.5 3.5
4.5
5.5
6.5
7.5
8.5
9.5
10 30
50
70
90 110 130 150 170 190
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
100K
10K
1.9
1.7
1.5
1.3
1.1
V
I
= 10 V
= 50 A
GS
T = 150°C
J
D
T = 125°C
J
T = 85°C
J
1K
0.9
0.7
100
−50 −25
0
25
50
75 100 125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMJS1D2N04CL
TYPICAL CHARACTERISTICS
10K
1K
10
C
ISS
8
6
4
C
OSS
Q
Q
GD
GS
100
10
V
= 32 V
= 50 A
DS
V
= 0 V
2
0
GS
C
RSS
I
D
T = 25°C
J
T = 25°C
J
f = 1 MHz
0
5
10
15
20
25
30
35
40
0
10
20 30 40 50 60 70 80 90 100
Q , TOTAL GATE CHARGE (nC)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
t
d(off)
V
GS
V
DS
= 10 V
= 32 V
V
GS
= 0 V
t
f
t
r
10
100
t
d(on)
T = 125°C T = 25°C
T = −55°C
J
J
J
10
1
1
10
R , GATE RESISTANCE (W)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
100
10
10 ms
T
= 25°C
J(initial)
Single Pulse
T
V
= 25°C
0.5 ms
1 ms
10 ms
T
= 100°C
C
J(initial)
≤ 10 V
GS
10
1
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMJS1D2N04CL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
0.01
Single Pulse
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMJS1D2N04CLTWG
1D2N04CL
LFPAK8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LFPAK8 5x6
CASE 760AA
ISSUE C
DATE 13 AUG 2019
GENERIC
MARKING DIAGRAM*
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
W
= Wafer Lot
= Year
= Work Week
XXXXXX
XXXXXX
AWLYW
*This information is generic. Please refer
to device data sheet for actual part
marking. Some products may not follow
the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON82475G
LFPAK8 5x6
PAGE 1 OF 1
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