NVMTS0D7N04CTXG [ONSEMI]
Power MOSFET, Single N-Channel, 40 V, 0.67 mOhms, 420 A;型号: | NVMTS0D7N04CTXG |
厂家: | ONSEMI |
描述: | Power MOSFET, Single N-Channel, 40 V, 0.67 mOhms, 420 A |
文件: | 总7页 (文件大小:356K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET – Power, Single
N-Channel
40 V, 0.67 mW, 420 A
NVMTS0D7N04C
Features
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• Small Footprint (8x8 mm) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
• Power 88 Package, Industry Standard
(BR)DSS
DS(ON)
• AEC−Q101 Qualified and PPAP Capable
• Wettable Flank Plated Option for Enhanced Optical Inspection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
40 V
0.67 mW @ 10 V
420 A
D (5−8)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
G (1)
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
420
297
205
103
65
A
S (2−4)
C
D
q
JC
N−CHANNEL MOSFET
T
C
(Notes 1, 3)
Steady
State
Power Dissipation
T
C
P
W
A
D
R
(Note 1)
q
JC
T
C
= 100°C
Continuous Drain
Current R
T = 25°C
A
I
D
q
JA
T = 100°C
A
46
(Notes 1, 2, 3)
Steady
State
Power Dissipation
T = 25°C
A
P
4.9
2.5
900
W
D
DFNW8
TX SUFFIX
CASE 507AP
R
(Notes 1, 2)
q
JA
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+ 175
°C
J
stg
MARKING DIAGRAM
Source Current (Body Diode)
I
S
171
A
Single Pulse Drain−to−Source Avalanche
E
AS
1446
mJ
Energy (I
= 40 A)
L(pk)
XXXXXXXX
AWLYWW
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
XXX = Device Code
(8 A−N characters max)
= Assembly Location
WL = 2−digit Wafer Lot Code
= Year Code
WW = Work Week Code
THERMAL RESISTANCE MAXIMUM RATINGS
A
Parameter
Symbol
Value
0.73
Unit
Y
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
30.4
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2020 − Rev. 4
NVMTS0D7N04C/D
NVMTS0D7N04C
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
20
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
10
DSS
GS
DS
J
V
= 40 V
mA
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
V
V
= V , I = 250 mA
2.0
4.0
V
mV/°C
mW
S
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
V
/T
J
−8.5
0.57
200
GS(TH)
R
V
GS
= 10 V
I = 50 A
D
0.67
DS(on)
g
FS
V =5 V, I = 50 A
DS D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
9281
5387
176
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 25 V
pF
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
V
GS
= 10 V, V = 20 V; I = 50 A
140
G(TOT)
DS
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
22.7
37
G(TH)
nC
V
Q
GS
GD
GP
V
GS
= 10 V, V = 20 V; I = 50 A
DS
D
Q
V
28.3
4.28
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
28.9
18.1
61.0
20.4
d(ON)
Rise Time
t
r
V
= 10 V, V = 20 V,
DS
GS
D
ns
V
I
= 50 A, R = 2.5 W
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T = 25°C
0.8
0.7
1.2
J
V
S
= 0 V,
GS
I
= 50 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
88.9
57.9
31
RR
t
a
ns
V
GS
= 0 V, dIS/dt = 100 A/ms,
I
= 50 A
S
Discharge Time
t
b
Reverse Recovery Charge
Q
191
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMTS0D7N04C
TYPICAL CHARACTERISTICS
1000
1000
900
800
700
600
500
400
300
200
7 V to 10 V
900
800
700
600
500
400
300
200
V
DS
= 3 V
6 V
T = 25°C
J
5 V
4 V
T = 125°C
J
100
0
100
0
T = −55°C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.0
0.9
0.8
0.7
0.6
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
T = 25°C
D
J
T = 25°C
GS
J
V
I
= 50 A
= 10 V
0.5
0.4
0.3
0.2
0.4
0.2
4
5
6
7
8
9
10
0
10
20
30 40
50 60 70 80 90 100
V
GS
, GATE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
T = 175°C
J
V
I
= 10 V
= 50 A
GS
T = 150°C
J
D
T = 125°C
J
T = 85°C
J
1.1
1.0
0.9
0.8
0.7
T = 25°C
J
1.E−08
1.E−09
−50 −25
0
25
50
75 100 125 150 175
5
10
15
, REVERSE VOLTAGE (V)
DS
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMTS0D7N04C
TYPICAL CHARACTERISTICS
100K
10K
1K
10
9
C
ISS
8
7
6
5
4
3
C
OSS
Q
Q
GD
GS
C
RSS
100
10
1
2
1
0
V
= 0 V
V
= 20 V
GS
DS
f = 1 MHz
I = 50 A
D
0.1
1
10
0
20
40
60
80
100
120
140
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Gate
Charge
1000
100
100
10
1
t
d(off)
V
GS
= 0 V
t
t
t
f
r
d(on)
0.1
10
1
T = 150°C
J
0.01
T = 25°C
T = −55°C
J
J
0.001
1
10
100
0
0.2
0.4
0.6
0.8
1.0
1.2
R , GATE RESISTANCE (W)
G
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
1000
100
10
10 ms
T
= 25°C
J(initial)
0.5 ms
1 ms
10 ms
T
= 25°C
C
T
= 100°C
J(initial)
Single Pulse
≤ 10 V
V
GS
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
0.00001
0.0001
0.001
0.01
1
10
100
TIME IN AVALANCHE (s)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMTS0D7N04C
100
10
50% Duty Cycle
20%
10%
5%
2%
1
1%
0.1
0.01
Single Pulse
0.001
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
POWER 88
Shipping
NVMTS0D7N04CTXG
0D7N04C
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TDFNW8 8.3x8.4, 2.0P, SINGLE COOL
CASE 507AP
ISSUE D
DATE 29 MAR 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A
= Assembly Location
WL = Wafer Lot Code
= Year Code
Y
WW = Work Week Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON80534G
TDFNW8 8.3x8.4, 2.0P, SINGLE COOL
PAGE 1 OF 1
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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