NVMTSC1D3N08M7TXG [ONSEMI]
Power MOSFET 80V, 348 A, 1.25mΩ, Single N-Channel;型号: | NVMTSC1D3N08M7TXG |
厂家: | ONSEMI |
描述: | Power MOSFET 80V, 348 A, 1.25mΩ, Single N-Channel 脉冲 光电二极管 晶体管 |
文件: | 总7页 (文件大小:405K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET - Power, Single
N-Channel
80 V, 1.25 mW, 348 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
80 V
1.25 mꢂ @ 10 V
348 A
D (5−8)
NVMTSC1D3N08M7
Features
• Small Footprint (8x8 mm) for Compact Design
G (1)
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
S (2−4)
N−CHANNEL MOSFET
• New Power 88 Dual Cool Package
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
• Wettable Flank Plated Option For Enhanced Optical Inspection
MARKING
DIAGRAM
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
80
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Continuous Drain
Current R
T
= 25°C
= 100°C
= 25°C
I
348
246
287
144
46
A
TDFNW8
CASE 507AR
C
D
ꢀ
JCB
1D3N08M AWLYW
T
C
(Notes 1, 3)
Steady
State
Power Dissipation
T
C
P
W
A
1D3N08M = Specific Device Code
= Assembly Location
WL = Wafer Lot Code
D
R
(Note 1)
A
ꢀ
JCB
T
C
= 100°C
Y
= Year Code
Continuous Drain
Current R
T = 25°C
A
I
D
W
= Work Week Code
ꢀ
JA
T = 100°C
A
33
(Notes 1, 2, 3)
Steady
State
Power Dissipation
T = 25°C
A
P
5.1
2.6
900
W
D
R
(Notes 1, 2)
ꢀ
JA
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ꢁ s
I
DM
A
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
Source Current (Body Diode)
I
S
239
A
Single Pulse Drain−to−Source Avalanche
E
AS
2228
mJ
Energy (I
= 28.2 A)
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
0.5
Unit
°C/W
°C/W
°C/W
Junction−to−Case Bottom − Steady State
Junction−to−Case Top − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
ꢀ
JCB
R
0.81
29
ꢀ
JCT
R
ꢀ
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
March, 2023 − Rev. 4
NVMTSC1D3N08M7/D
NVMTSC1D3N08M7
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 ꢁ A
80
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
31.4
(BR)DSS
mV/°C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25 °C
1
DSS
GS
DS
J
V
= 80 V
ꢁ
A
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
GS
V
V
= V , I = 250 ꢁ A
2.0
4.0
V
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
V
/T
−10
0.97
253
mV/°C
GS(TH)
J
R
V
= 10 V
I = 80 A
D
1.25
mꢂ
DS(on)
GS
g
FS
V
=15 V, I = 80 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
14530
2047
106
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 40 V
pF
GS
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
V
GS
= 10 V, V = 40 V; I = 80 A
196
G(TOT)
DS
D
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
37.3
68.3
36.4
4.82
G(TH)
nC
V
Q
GS
GD
GP
V
GS
= 10 V, V = 40 V; I = 80 A
DS
D
Q
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
t
39.9
29.0
80.9
32.8
d(ON)
Rise Time
t
r
V
= 10 V, V = 40 V,
DS
GS
D
ns
V
I
= 80 A, R = 2.5 ꢂ
G
Turn−Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.80
0.68
80.3
50
1.2
SD
J
V
S
= 0 V,
GS
I
= 80 A
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
a
V
= 0 V, dIS/dt = 100 A/ꢁ s,
GS
I
S
= 80 A
Discharge Time
t
30
b
Reverse Recovery Charge
Q
152
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ꢁ s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMTSC1D3N08M7
TYPICAL CHARACTERISTICS
350
315
280
245
210
175
140
105
70
V
= 6.0 V
GS
V
= 10 V
DS
300
200
10 to 8.0 V
5.0 V
4.8 V
T = 25°C
J
100
0
4.4 V
4.0 V
35
0
T = 125°C
J
T = −55°C
J
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
, DRAIN−TO−SOURCE VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
V
DS
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.2
1.1
1.0
0.9
0.8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I
= 80 A
D
T = 25°C
J
T = 25°C
J
V
GS
= 10 V
0.7
0.6
0.5
0
4
5
6
7
8
9
10
5
50
95 140 185 230 275 320 365 410
I , DRAIN CURRENT (A)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1M
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
T = 175°C
J
I
V
= 80 A
D
100K
10K
1K
= 10 V
GS
T = 150°C
J
T = 125°C
J
T = 85°C
J
100
10
1
T = 25°C
J
0.2
0
−55 −35 −15
5
25 45 65 85 105 125 145 165
0
10
20
30
40
50
60
70
80
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMTSC1D3N08M7
TYPICAL CHARACTERISTICS
10
100K
10K
1K
V
DS
= 40 V
9
8
7
6
5
4
3
2
C
C
iss
I
D
= 80 A
T = 25°C
J
oss
Q
Q
GS
GD
100
C
rss
T = 25°C
GS
f = 1 MHz
10
1
J
V
= 0 V
1
0
0.1
1
10
100
0
20 40
60
80 100 120 140 160 180
Q , TOTAL GATE CHARGE (nC)
G
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
100
10
1000
100
t
f
V
= 0 V
GS
t
t
d(off)
t
r
T = 125°C
J
d(on)
T = 150°C
J
1
10
1
T = 175°C
J
V
V
= 10 V
= 40 V
= 80 A
GS
T = 25°C
J
DS
I
D
T = −55°C
J
0.1
1
10
R , GATE RESISTANCE (ꢂ)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
, SOURCE−TO−DRAIN VOLTAGE (V)
V
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
T
= 25°C
J(initial)
10 ꢁ s
100
10
1
10
T
V
= 25°C
≤ 10 V
C
T
= 100°C
J(initial)
GS
Single Pulse
0.5 ms
1 ms
1
10 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMTSC1D3N08M7
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
0.01
Single Pulse
0.000001 0.00001
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMTSC1D3N08M7TXG
1D3N08M
TDFNW8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TDFNW8 8.3x8.4, 2P, DUAL COOL, OPTION 2
CASE 507AR
ISSUE B
DATE 29 MAR 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A
= Assembly Location
WL = Wafer Lot Code
Y
= Year Code
W
= Work Week Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON95711G
TDFNW8 8.3x8.4, 2P, DUAL COOL, OPTION 2
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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