P3PS550AHG-08CR [ONSEMI]

High Drive General Purpose Peak EMI Reduction IC; 高驱动通用峰值EMI降低IC
P3PS550AHG-08CR
型号: P3PS550AHG-08CR
厂家: ONSEMI    ONSEMI
描述:

High Drive General Purpose Peak EMI Reduction IC
高驱动通用峰值EMI降低IC

晶体 时钟发生器 微控制器和处理器 外围集成电路 光电二极管 驱动
文件: 总6页 (文件大小:114K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
P3PS550AH  
High Drive General Purpose  
Peak EMI Reduction IC  
Product Description  
The P3PS550AH is a versatile 2.3 V to 3.6 V, TimingSafe, high  
drive spread spectrum frequency modulator designed specifically for a  
wide range of clock frequencies. The P3PS550AH reduces  
electromagnetic interference (EMI) at the clock source, allowing  
system wide reduction of EMI of all clock dependent signals. The  
P3PS550AH allows significant system cost savings by reducing the  
number of circuit board layers ferrite beads, shielding that are  
traditionally required to pass EMI regulations.  
http://onsemi.com  
MARKING  
DIAGRAMS  
1
1
CCMG  
G
WDFN8  
CASE 511AQ  
Features  
High Drive, LVCMOS Peak EMI reduction IC  
Input Clock Frequency: 18 MHz 36 MHz  
Output Clock Frequency: 18 MHz 36 MHz  
Eight different selectable Spread options  
Power Down option for power save  
Supply Voltage: 2.3 V 3.6 V  
8pin WDFN, 2 mm x 2 mm (TDFN) Package  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
CC = Specific Device Code  
M
= Date Code  
G
= PbFree Device  
PIN CONFIGURATION  
1
2
3
4
8
CLKIN  
SR2  
VDD  
Applications  
7
SR0  
P3PS550AH  
The P3PS550AH is targeted towards consumer electronic  
PD#  
6
5
SR1  
applications.  
ModOUT  
VSS  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2010  
1
Publication Order Number:  
July, 2010 Rev. 1  
P3PS550AH/D  
P3PS550AH  
VDD  
SR1  
SR2  
SR0  
ModOUT  
PLL  
CLKIN  
PD#  
VSS  
Figure 1. Block Diagram  
P3PS550AH modulates the output of a single PLL in  
order to “spread” the bandwidth of a synthesized clock, and  
more importantly, decreases the peak amplitudes of its  
harmonics. This results in significantly lower system EMI  
compared to the typical narrow band signal produced by  
oscillators and most frequency generators. Lowering EMI  
by increasing a signal’s bandwidth is called ‘spread  
spectrum clock generation’.  
P3PS550AH accepts an input from an external reference  
clock and locks to a 1x modulated clock output. SR0, SR1  
and SR2 pins enable selecting one of the eight different  
frequency deviations (Refer Frequency Deviation Selection  
table). P3PS550AH also features power down option for  
power save. P3PS550AH operates over a supply voltage  
range of 2.3 V to 3.6 V. P3PS550AH is available in an 8 Pin  
WDFN, (2 mm x 2 mm) Package.  
Table 1. PIN DESCRIPTION  
Pin#  
Pin Name  
CLKIN  
SR2  
Type  
Description  
1
2
I
I
External reference clock input.  
Digital logic input used to select Spreading Range. There is NO default state.  
Refer Frequency Deviation Selection Table.  
3
PD#  
I
Powerdown control pin. Powers down the entire chip. There is NO default state. Pull low to en-  
able powerdown mode. Connect to VDD to disable Power Down.  
Output Clock will be LOW when power down is enabled  
4
5
6
VSS  
ModOUT  
SR1  
P
O
I
Ground connection.  
Spread Spectrum Clock Output.  
Digital logic input used to select Spreading Range. This pin has an internal pullup resistor. Refer  
Modulation Selection Table.  
7
8
SR0  
VDD  
I
Digital logic input used to select Spreading Range. There is NO default state.  
Refer Frequency Deviation Selection Table.  
P
Power supply for the entire chip  
http://onsemi.com  
2
P3PS550AH  
Table 2. FREQUENCY DEVIATION SELECTION TABLE  
Spreading Range ($ %)  
(@ 24 MHz)  
SR2  
0
SR1  
0
SR0  
0
1
0
0
1
2.5  
1.25  
1.5  
0.4  
0.75  
1.75  
2
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 3. OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
2.3  
Max  
3.6  
+85  
15  
Unit  
V
V
Supply Voltage with respect to VSS  
Operating temperature  
Load Capacitance  
DD  
T
20  
°C  
pF  
pF  
A
C
L
C
Input Capacitance  
7
IN  
Table 4. ABSOLUTE MAXIMUM RATING  
Symbol  
Parameter  
Rating  
Unit  
V
V
DD  
, V  
IN  
Voltage on any input pin with respect to V  
SS  
0.5 to +4.6  
T
Storage temperature  
65 to +125  
°C  
°C  
°C  
kV  
STG  
T
s
Max. Soldering Temperature (10 sec)  
Junction Temperature  
260  
150  
2
T
J
T
Static Discharge Voltage (As per JEDEC STD22A114B)  
DV  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may  
affect device reliability.  
Table 5. DC ELECTRICAL CHARACTERISTICS  
Symbol  
Parameter  
Supply Voltage with respect to V  
Min  
2.3  
Typ  
Max  
Unit  
V
VDD  
2.8  
3.6  
SS  
V
Input high voltage  
Input low voltage  
0.65 * V  
V
IH  
DD  
V
0.3 * V  
50  
V
IL  
DD  
I
IH  
Input high current (SR1 control pin)  
Input low current (SR1 control pin)  
mA  
mA  
V
I
IL  
50  
V
OH  
Output high voltage (I = 16 mA)  
0.75 * V  
OH  
DD  
V
Output low voltage (I = 16 mA)  
0.2 * V  
V
OL  
CC  
DD  
OL  
DD  
I
I
Static supply current (PD# pulled to V  
)
1
9
mA  
mA  
W
SS  
Dynamic supply current (Unloaded Output @ 24 MHz)  
Output impedance  
6
Z
OUT  
20  
http://onsemi.com  
3
P3PS550AH  
Table 6. AC ELECTRICAL CHARACTERISTICS  
Symbol  
CLKIN  
Parameter  
Min  
18  
Typ  
24  
Max  
36  
Unit  
MHz  
MHz  
ns  
Input Clock frequency  
Output Clock frequency  
Output rise time  
ModOUT  
18  
24  
36  
t
t
(Note 1)  
(Note 1)  
Unloaded Output  
0.4  
1.4  
0.3  
1.1  
$175  
50  
0.8  
2.2  
0.6  
1.9  
$250  
55  
LH  
(Measured between 20% to 80%)  
C = 15 pF  
L
Output fall time  
Unloaded Output  
ns  
HL  
(Measured between 80% to 20%)  
C = 15 pF  
L
t
(Note 1)  
(Note 1)  
(Note 1)  
Jitter (cycle to cycle) Unloaded Output  
Output duty cycle  
ps  
%
JC  
t
45  
D
t
PLL lock Time  
3
ms  
ON  
(Stable power supply, valid clock presented on CLKIN pin,  
PD# toggled from Low to High)  
fd  
Frequency Deviation Variation across PVT  
$2.5  
$5  
%
var  
1. Parameter is guaranteed by design and characterization. Not 100% tested in production  
VDDIN  
R
C1  
C2  
0.1mF  
2.2mF  
8
M Clock  
VDD  
CLKIN  
1
P3PS550AH  
Rs  
ModOUT Clock  
5
3
ModOUT  
PD#  
VDD  
0 W  
0 W  
VDD  
SR2, SR1, SR0  
Frequency Deviation  
Selection Control  
0 W  
0 W  
SR2/SR1/SR0  
Power Down  
Control  
2,6,7  
VSS  
4
NOTE: Refer Pin Description table for Functionality details.  
Figure 2. Typical Application Schematic  
PCB Layout Recommendation  
For optimum device performance, following guidelines are recommended.  
Dedicated VDD and GND planes.  
The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be  
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the  
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.  
All the VDD pins should have decoupling capacitors.  
In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.  
A typical layout is shown in the figure  
http://onsemi.com  
4
 
P3PS550AH  
As short as  
possible  
R
As short as  
possible  
CLKIN  
SR2  
VDD  
SR0  
SR1  
PD#  
VSS  
Rs  
Modout  
Figure 3.  
ORDERING INFORMATION  
Part Number  
Top Marking  
CC  
Temperature  
Package Type  
Shipping  
P3PS550AHG08CR  
20°C to +85°C  
8pin (2 mm x 2 mm)  
Tape & Reel  
WDFN  
http://onsemi.com  
5
P3PS550AH  
PACKAGE DIMENSIONS  
WDFN8 2x2, 0.5P  
CASE 511AQ01  
ISSUE A  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.15 AND 0.30mm FROM TERMINAL.  
D
A
B
L
L
L1  
PIN ONE  
DETAIL A  
MILLIMETERS  
REFERENCE  
2X  
E
OPTIONAL  
DIM  
A
MIN  
0.70  
0.00  
MAX  
0.80  
0.05  
CONSTRUCTIONS  
0.10  
C
A1  
A3  
b
0.20 REF  
0.20  
0.30  
0.10  
C
2X  
D
2.00 BSC  
EXPOSED Cu  
MOLD CMPD  
TOP VIEW  
E
2.00 BSC  
0.50 BSC  
e
L
0.50  
---  
0.60  
0.15  
A3  
DETAIL B  
L1  
0.05  
C
C
DETAIL B  
OPTIONAL  
A
8X  
CONSTRUCTION  
0.05  
A1  
RECOMMENDED  
SOLDERING FOOTPRINT*  
SEATING  
PLANE  
C
SIDE VIEW  
7X  
0.78  
DETAIL A  
1
PACKAGE  
OUTLINE  
8X L  
4
2.30  
0.88  
8
5
8X b  
1
0.50  
e/2  
e
8X  
0.35  
0.10  
C
A
B
PITCH  
NOTE 3  
0.05  
C
DIMENSIONS: MILLIMETERS  
BOTTOM VIEW  
*For additional information on our PbFree strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
TimingSafe is a trademark of Semiconductor Components Industries, LLC (SCILLC).  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 8002829855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81357733850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 3036752175 or 8003443860 Toll Free USA/Canada  
Fax: 3036752176 or 8003443867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
P3PS550AH/D  

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