P3PS850BH [ONSEMI]
Timing-Safe Peak EMI Reduction IC; 时序安全山顶降低EMI IC
| 型号： | P3PS850BH |
| 厂家： | 
ONSEMI |
| 描述： | Timing-Safe Peak EMI Reduction IC |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P3PS850BH
Timing-Safe] Peak EMI
Reduction IC
Functional Description
P3PS850BH is a versatile, Timing−Safe peak EMI reduction IC.
P3PS850BH accepts one input from an external reference, and locks
on to it delivering a 1x Timing−Safe output clock. P3PS850BH has a
Frequency Selection (FS) control that facilitates selecting one of the
two operating frequency ranges. Refer to the frequency Selection
table. The device has an SSEXTR pin to select different deviations
depending upon the value of an external resistor connected at this pin
to GND. P3PS850BH has an MR pin for selecting one of the two
Modulation Rates. PD#/OE provides the Power Down option. Outputs
will be tri−stated when power down is active.
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MARKING
DIAGRAMS
1
1
DGMG
G
WDFN8
CASE 511AQ
P3PS850BH operates over a supply voltage range of 2.3 V to 3.6 V,
and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
DG = Specific Device Code
M
= Date Code
G
= Pb−Free Device
General Features
• 1x , LVCMOS Timing−Safe Peak EMI Reduction
• Input Clock Frequency:
♦ 18 MHz − 72 MHz
PIN CONFIGURATION
• Output Clock Frequency( Timing−Safe):
♦ 18 MHz − 72 MHz
CLKIN
PD#/OE
FS
1
8
7
6
5
V
DD
• Analog Frequency Deviation Selection
• Two different Modulation Rate Selection
• Power Down Option for Power Save
• Output Buffer Strength: 16 mA
• Supply Voltage: 2.3 V − 3.6 V
• 8 pin WDFN 2 mm x 2 mm, (TDFN) Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
2
3
4
SSEXTR
MR
P3PS850BH
GND
ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Application
• P3PS850BH is targeted for use in consumer electronic applications
like mobile phones, Camera modules, MFP and DPF.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
January, 2012 − Rev. 1
P3PS850BH/D
P3PS850BH
V
DD
MR
SSEXTR
CLKIN
PLL
ModOUT
(Timing−Safe)
FS
PD#/OE
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
Pin Name
CLKIN
Type
Description
1
2
I
I
External reference Clock input.
PD# / OE
Power Down. Pull LOW to enable Power Down. Outputs will be tri−stated when power down is en-
abled. Pull HIGH to disable power down and enable output. NO default state.
3
4
5
6
FS
GND
I
P
O
I
Frequency Select .NO default state. Refer to the Frequency Selection table
Ground
ModOUT
MR
Buffered modulated Timing−Safe clock output
Modulation Rate Select. When LOW, selects Low Modulation Rate. Selects High
Modulation Rate when pulled HIGH. Has an internal pull−up resistor.
7
8
SSEXTR
I
Analog Deviation Selection through external resistor to GND.
Supply Voltage
V
DD
P
Table 2. FREQUENCY SELECTION TABLE
FS
0
Frequency (MHz)
18−36
1
36−72
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Min
2.3
Max
3.6
+85
15
Unit
V
V
DD
Supply Voltage
T
Operating Temperature
Load Capacitance
Input Capacitance
−20
°C
pF
pF
A
C
L
C
7
IN
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2
P3PS850BH
Table 4. ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Rating
−0.5 to +4.6
−65 to +125
260
Unit
V
V
V
Voltage on any input pin with respect to Ground
Storage temperature
DD, IN
T
°C
°C
°C
kV
STG
T
Max. Soldering Temperature (10 sec)
Junction Temperature
s
T
J
150
T
DV
Static Discharge Voltage (As per JEDEC STD22−A114−B)
2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Supply Voltage
Test Conditions
Min
2.3
Typ
Max
Unit
V
V
DD
2.7
3.6
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
Output LOW Voltage
Static Supply Current
Dynamic Supply Current
0.65 * V
V
IH
DD
V
0.35 * V
10
V
IL
DD
I
IH
V
V
= V
DD
mA
mA
V
IN
I
IL
= 0 V for MR pin
= −16 mA
10
IN
V
OH
I
0.75 * V
OH
OL
DD
V
I
= 16 mA
0.25 * V
10
V
OL
CC
DD
DD
I
I
PD#/OE pin pulled to GND
Unloaded Output
FS = 0, @ 18 MHz
mA
mA
6
7
10
FS = 0, @ 24 MHz
FS = 0, @ 36 MHz
FS = 1, @ 36 MHz
FS = 1, @ 48 MHz
FS = 1, @ 72 MHz
12
10
9
17
14
11
16
13
19
28
Z
Output Impedance
W
o
Table 6. AC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
18
36
18
36
45
Typ
24
Max
36
Unit
Input Frequency
FS = 0
MHz
FS = 1
FS = 0
FS = 1
48
72
ModOUT
24
36
48
72
Duty Cycle (Note 1 and 2)
Rise Time (Note 1 and 2)
Measured at V / 2
50
55
%
ns
ns
DD
Measured between 20% to 80%
Measured between 80% to 20%
0.8
0.8
1.2
1.2
)
Fall Time (Note 1 and 2
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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3
P3PS850BH
Table 6. AC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
$350
$225
$125
$200
$150
$125
1
Unit
Cycle−to−Cycle Jitter (Note 2)
Unloaded output
with SSEXTR pin
OPEN
FS = 0, 18 MHz
$250
$150
$75
$150
$100
$75
ps
FS = 0, 24 MHz
FS = 0, 36 MHz
FS = 1, 36 MHz
FS = 1, 48 MHz
FS = 1, 72 MHz
PLL Lock Time (Note 2)
Stable power supply, valid clock presen-
ted on CLKIN pin, PD# toggled from Low
to High
ms
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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4
P3PS850BH
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.5
2.0
1.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
MR = 0
MR = 0
1.0
0.5
MR = 1
MR = 1
0.0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTOR (kW)
RESISTOR (kW)
Figure 2. Deviation vs. SSEXTR @ 18 MHz
(FS = 0)
Figure 3. Deviation vs. SSEXTR @ 24 MHz
(FS = 0)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
MR = 0
MR = 1
MR = 0
MR = 1
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTOR (kW)
RESISTOR (kW)
Figure 4. Deviation vs. SSEXTR @ 27 MHz
(FS = 0)
Figure 5. Deviation vs. SSEXTR @ 30 MHz
(FS = 0)
3.0
2.5
2.0
1.5
1.0
MR = 0
0.5
MR = 1
0.0
0
100 200 300 400 500 600 700 800 900 1000
RESISTOR (kW)
Figure 6. Deviation vs. SSEXTR @ 36 MHz
(FS = 0)
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5
P3PS850BH
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
MR = 0
MR = 0
MR = 1
100
MR = 1
0.5
0.0
0
200
300
400
500
600
0
100
200
300
400
500
600
RESISTOR (kW)
RESISTOR (kW)
Figure 7. Deviation vs. SSEXTR @ 36 MHz
(FS = 1)
Figure 8. Deviation vs. SSEXTR @ 48 MHz
(FS = 1)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
MR = 0
MR = 1
MR = 1
MR = 0
0
100
200
300
400
500
600
0
100
200
300
400
500
600
RESISTOR (kW)
RESISTOR (kW)
Figure 9. Deviation vs. SSEXTR @ 54 MHz
(FS = 1)
Figure 10. Deviation vs. SSEXTR @ 60 MHz
(FS = 1)
3.0
2.5
2.0
1.5
1.0
MR = 0
0.5
MR = 1
0.0
0
100
200
300
400
500
600
RESISTOR (kW)
Figure 11. Deviation vs. SSEXTR @ 72 MHz
(FS = 1)
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6
P3PS850BH
TSKEW VERSUS SSEXTR RESISTANCE CHARTS
25
20
15
10
5
18
16
14
12
10
8
MR = 0
6
MR = 0
4
2
MR = 1
MR = 1
0
0
0
100 200 300 400 500 600 700 800 900 10001100
0
100 200 300 400 500 600 700 800 900 10001100
RESISTOR (kW)
Figure 12. Tskew vs. SSEXTR @ 18 MHz
(FS = 0)
RESISTOR (kW)
Figure 13. Tskew vs. SSEXTR @ 24 MHz
(FS = 0)
16
14
12
10
8
12
10
8
6
6
4
4
MR = 0
MR = 0
2
2
MR = 1
MR = 1
0
0
0
100 200 300 400 500 600 700 800 900 10001100
0
100 200 300 400 500 600 700 800 900 10001100
RESISTOR (kW)
Figure 14. Tskew vs. SSEXTR @ 27 MHz
(FS = 0)
RESISTOR (kW)
Figure 15. Tskew vs. SSEXTR @ 36 MHz
(FS = 0)
12
10
9
8
7
6
5
4
3
2
1
0
10
8
6
MR = 0
MR = 0
4
2
MR = 1
MR = 1
0
0
100 200 300 400 500 600 700 800 900 10001100
0
100 200 300 400 500 600 700 800 900 10001100
RESISTOR (kW)
RESISTOR (kW)
Figure 16. Tskew vs. SSEXTR @ 36 MHz
(FS = 1)
Figure 17. Tskew vs. SSEXTR @ 48 MHz
(FS = 1)
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P3PS850BH
TSKEW VERSUS SSEXTR RESISTANCE CHARTS
8
7
6
5
4
3
2
1
0
6
5
4
3
MR = 0
2
1
0
MR = 0
MR = 1
MR = 1
0
100 200 300 400 500 600 700 800 900 10001100
0
100 200 300 400 500 600 700 800 900 10001100
RESISTOR (kW)
RESISTOR (kW)
Figure 18. Tskew vs. SSEXTR @ 54 MHz
(FS = 1)
Figure 19. Tskew vs. SSEXTR @ 72 MHz
(FS = 1)
MINIMUM SSEXTR RESISTANCE VERSUS FREQUENCY(FOR TIMING−SAFE OPERATION) CHARTS
50
45
40
35
30
25
20
15
10
5
120
110
100
90
80
70
60
50
40
30
20
10
0
MR = 0
MR = 0
MR = 1
MR = 1
0
18
20
22
24
26
28
30
32
34
36
36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Frequency vs. Resistance
(FS = 0)
Figure 21. Frequency vs. Resistance
(FS = 1)
NOTE: Device−to−Device variation of Deviation and Tskew is $10%
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8
P3PS850BH
SWITCHING WAVEFORMS
t
1
t
2
V
/2
V
/2
DD
DD
V
/2
DD
OUTPUT
Figure 22. Duty Cycle Timing
80%
20%
80%
20%
OUTPUT
t
3
t
4
Figure 23. Output Rise/Fall Time
Timing−Safe
Input
Output
T
SKEW
T
T
SKEW/2
SKEW/2
One clock cycle (T)
represents input−output skew
T
SKEW
when spread spectrum is ON
For example, T / 2 = 0.20 * T for an
SKEW
Input clock of 24 MHz, translates in to
(1/24 MHz) * 0.20 = 8.33 ns
Figure 24. Input−Output Skew
Input
Input
Timing-Safe ModOUT
ModOUT with SSOFF
Figure 25. Typical Example of Timing−Safe Waveform
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P3PS850BH
Recommended Noise
reduction Filter
VDDIN
R
0.1 mF C1
2.2 mF C2
8
CLKIN
V
DD
CLKIN
1
2
Rs
Rx
V
DD
ModOUT Clock
ModOUT
SSEXTR
5
7
Power down
Control
PD#/OE
Analog Deviation Control
V
DD
P3PS850BH
V
DD
Frequency Selection
Control
3
FS
Modulation Rate
Control
MR
6
GND
4
NOTE: Refer Pin Description table for Functionality details.
Figure 26. Typical Application Schematic
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10
P3PS850BH
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated V and GND planes.
DD
• The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the V pin as possible. No vias should be used between the
DD
decoupling capacitor and V pin. The PCB trace to V pin and the ground via should be kept as short as possible.
DD
DD
All the V pins should have decoupling capacitors.
DD
• In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in Figure 27.
As short as
possible
R
As short as
possible
CLKIN
VDD
PD#/OE
FS
SSEXTR
MR
Rs
Modout
GND
Figure 27.
ORDERING INFORMATION
Top
Marking
†
Part Number
Temperature
Package Type
Shipping
P3PS850BHG−08CR
DG
−20°C to +85°C
8−Pin (2 mm x 2 mm) WDFN(TDFN)
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free.
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11
P3PS850BH
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
D
A
B
L
L
L1
PIN ONE
DETAIL A
MILLIMETERS
REFERENCE
2X
E
OPTIONAL
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
CONSTRUCTIONS
0.10
C
A1
A3
b
0.20 REF
0.20
0.30
0.10
C
2X
D
2.00 BSC
EXPOSED Cu
MOLD CMPD
TOP VIEW
E
2.00 BSC
0.50 BSC
e
L
0.50
---
0.60
0.15
A3
DETAIL B
L1
0.05
C
C
DETAIL B
OPTIONAL
A
8X
CONSTRUCTION
0.05
A1
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
SIDE VIEW
7X
0.78
DETAIL A
1
PACKAGE
OUTLINE
8X L
4
2.30
0.88
8
5
8X b
1
0.50
e/2
e
8X
0.35
0.10
C
A
B
PITCH
NOTE 3
0.05
C
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
P3PS850BH/D
相关型号：
P3PSL450AHG-08CR
Peak Emi Reduction IC, Low Voltage, Timing-Safe™, WDFN8 2x2, 0.5P, 3000-REEL
ONSEMI
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