P3PSL450AHG-08CR [ONSEMI]
Peak Emi Reduction IC, Low Voltage, Timing-Safe™, WDFN8 2x2, 0.5P, 3000-REEL;
| 型号： | P3PSL450AHG-08CR |
| 厂家： | 
ONSEMI |
| 描述： | Peak Emi Reduction IC, Low Voltage, Timing-Safe™, WDFN8 2x2, 0.5P, 3000-REEL 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P3PSL450A
Low Voltage, Timing-Safe]
Peak EMI Reduction IC
Functional Description
P3PSL450A/AH is a versatile low voltage peak EMI reduction IC
based on Timing−Safe technology. P3PSL450A/AH accepts one input
from an external reference, and locks on to it delivering a 1x
Timing−Safe output clock. P3PSL450A/AH has a Frequency
Selection (FS) control that facilitates selecting one of the two
frequency ranges within the operating frequency range. Refer
frequency Selection table. The device has an SSEXTR pin to select
different deviations depending upon the value of an external resistor
connected at this pin to GND. P3PSL450A/AH has an MR pin for
selecting one of the two Modulation Rates. PD# provides the Power
Down option.
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MARKING
DIAGRAM
1
XX MG
1
G
WDFN8
CASE 511AQ
P3PSL450A is a Low drive part and P3PSL450AH is a High drive
part. Refer to DC/AC Electrical characteristic table.
XX = Specific Device Code
M
= Date Code
P3PSL450A/AH operates over a supply voltage range of 1.8 V $
G
= Pb−Free Device
0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
General Features
PIN CONFIGURATION
• 1x, LVCMOS Timing−Safe Peak EMI Reduction
• Input Clock Frequency: 15 MHz − 60 MHz
• Output Clock Frequency (Timing−Safe): 15 MHz − 60 MHz
• Analog Frequency Deviation Selection
• Two different Modulation Rate Selection Option
• Power Down option for Power Save
• Low and High Drive Parts
CLKIN
FS
1
2
3
4
8
7
6
5
VDD
SSEXTR
MR
PD#
GND
ModOUT
• Supply Voltage: 1.8 V $ 0.2 V
• 8 Pin WDFN (2 mm X 2 mm) Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Compliant
Application
• P3PSL450A/AH is targeted for use in consumer electronic
applications like mobile phones, Camera modules, MFP and DPF
MR
SSEXTR
VDD
CLKIN
PLL
ModOUT
(Timing−Safe)
GND
PD#
FS
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
July, 2010 − Rev. 1
P3PSL450A/D
P3PSL450A
Table 1. PIN DESCRIPTION
Pin #
Pin Name
CLKIN
FS
Type
Description
1
2
3
I
I
I
External reference Clock input.
Frequency Select. Has an internal pull−down resistor. see Frequency Selection table
PD#
Power Down. Pull LOW to enable Power Down. Pull HIGH to disable power down.
Output Clock will be LOW when power down is enabled. Has an internal pull−up resistor
4
5
6
GND
ModOUT
MR
P
O
I
Ground
Buffered modulated Timing−Safe clock output
Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High
Modulation Rate when pulled HIGH. Has an internal pull−up resistor.
7
8
SSEXTR
VDD
I
Analog Frequency Deviation Selection through external resistor to GND.
1.8 V Supply Voltage
P
Table 2. FREQUENCY SELECTION TABLE
FS
0
Frequency (MHz)
15−30
1
30−60
Table 3. ABSOLUTE MAXIMUM RATING
Parameter
Min
−0.3
−0.3
−0.3
−65
Max
+2.7
+2.7
Unit
V
Supply Voltage to Ground Potential
DC Input Voltage(CLKIN)
V
DC Input Voltage (Except CLKIN)
Storage Temperature
V
+ 0.3
V
DD
+150
260
°C
°C
°C
V
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
(As per JEDEC STD22−A114−B)
2000
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. OPERATING CONDITIONS
Symbol
Parameter
Min
1.6
Max
2
Unit
V
V
DD
Supply Voltage
T
Operating Temperature
Load Capacitance
Input Capacitance
−20
+85
15
7
°C
pF
pF
A
C
L
C
IN
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2
P3PSL450A
Table 5. DC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Symbol
Parameter
Test Conditions
Min
1.6
Typ
Max
Unit
V
VDD
Supply Voltage
1.8
2
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
0.65 * V
V
IH
DD
V
0.35 * V
V
IL
DD
I
IH
V
= V
DD
5
5
mA
mA
V
IN
I
IL
V
= 0 V
IN
V
OH
I
= −8 mA (P3PSL450A)
0.75 * V
OH
DD
I
= −16 mA (P3PSL450AH)
OH
V
OL
Output LOW Voltage
I
OL
= 8 mA (P3PSL450A)
0.25 * V
DD
V
I
OL
= 16 mA (P3PSL450AH)
I
I
Static Supply Current
CLKIN & PD# pins pulled to GND
10
2.2
3.7
3.7
6.4
mA
CC
Dynamic Supply Current
Unloaded
Output
FS = 0, @ 15 MHz
FS = 0, @ 30 MHz
FS = 1, @ 30 MHz
FS = 1, @ 60 MHz
1.7
3.0
2.6
4.3
23
mA
DD
Z
Output Impedance
P3PSL450A
P3PSL450AH
W
o
17
Table 6. AC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Parameter
Test Conditions
Min
15
30
15
30
45
Typ
Max
30
Unit
Input Frequency
FS = 0
MHz
FS = 1
60
ModOUT
FS = 0
30
FS = 1
60
Duty Cycle
(Notes 1 and 2)
Measured at V / 2
50
55
%
DD
Rise Time
Measured between 20% to
P3PSL450A
P3PSL450AH
P3PSL450A
P3PSL450AH
1.3
1
2.1
1.7
2.1
1.7
ns
(Notes 1 and 2)
80%
Fall Time
(Notes 1 and 2)
Measured between 80% to
20%
1.3
ns
ps
1
Cycle−to−Cycle Jitter
(Note 2)
Unloaded output with
SSEXTR pin OPEN
FS = 0
15 MHz
$150
$100
$80
$150
$100
$250
$150
$150
$250
$150
1
24 MHz
30 MHz
30 MHz
60 MHz
FS = 1
2
PLL Lock Time
Stable power supply, valid clock presented on CLKIN pin,
PD# toggled from Low to High
ms
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
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3
P3PSL450A
SWITCHING WAVEFORMS
t
1
t
2
V
DD
/2
V
DD
/2
V
DD
/2
OUTPUT
Figure 2. Duty Cycle Timing
80%
80%
20%
20%
OUTPUT
t
3
t
4
Figure 3. Output Rise/Fall Time
Input
Timing−Safe Output
T
SKEW
T
T
SKEW/2
T
SKEW/2
One clock cycle (T)
represents input−output skew when spread spectrum is ON
SKEW
For example, T
= $0.20 * T for an Input clock of 24 MHz, translates in to
SKEW/2
(1/24 MHz) * 0.20 = 8.33 ns
Figure 4. Input−Output Skew
Input
Input
Timing-Safe ModOUT
ModOUT with SSOFF
Figure 5. Typical Example of Timing−Safe Waveform
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4
P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
FS = 0,
MR = 0
FS = 0,
MR = 1
2.5
2.0
1.5
1.0
0.5
0.0
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 6. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
Figure 7. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
3
2.5
2
3
FS = 0,
MR = 0
FS = 0,
MR = 1
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 8. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
Figure 9. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
2.5
2.0
1.5
1.0
0.5
0.0
1.5
1.0
0.5
0.0
FS = 0,
MR = 0
FS = 0,
MR = 1
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 10. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
Figure 11. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
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5
P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
FS = 1,
MR = 0
FS = 1,
MR = 1
2.5
2.0
1.5
1.0
0.5
0.0
0
100 200 300 400 500 600 700 800 900 1000
0
0
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 12. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
RESISTANCE (kW)
Figure 13. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
FS = 1,
MR = 0
FS = 1,
MR = 1
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 14. Deviation vs SSEXTR Chart
(CLKIN = 48 MHz)
RESISTANCE (kW)
Figure 15. Deviation vs SSEXTR Chart
(CLKIN = 48 MHz)
2.5
2.0
1.5
1.0
0.5
0.0
1.5
1.0
0.5
0.0
FS = 1,
MR = 0
FS = 1,
MR = 1
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 16. Deviation vs SSEXTR Chart
(CLKIN = 60 MHz)
RESISTANCE (kW)
Figure 17. Deviation vs SSEXTR Chart
(CLKIN = 60 MHz)
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6
P3PSL450A
Recommended Noise
reduction Filter
VDDIN
R
0.1 mF
2.2 mF
C1
C2
8
VDD
1 CLKIN
Rs
Rx
VDD
ModOUT Clock
5
ModOUT
Frequency Selection
Control
P3PSL450A/AH
SSEXTR
2 FS
Analog Deviation Control.
SSEXTR can be Pulled HIGH
to turn OFF SS.
7
6
VDD
VDD
Power down
Control
3
PD#
Modulation Rate
Control
MR
GND
4
NOTE: Refer to Pin Description table for Functionality details
Figure 18. Typical Application Schematic
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7
P3PSL450A
PCB LAYOUT RECOMMENDATION
For optimum device performance, following guidelines are recommended.
• Dedicated V and GND planes.
DD
• The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the V pin as possible. No vias should be used between the
DD
decoupling capacitor and V pin. The PCB trace to V pin and the ground via should be kept as short as possible.
DD
DD
All the V pins should have decoupling capacitors.
DD
• In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the Figure below:
As short as
possible
R
As short as
possible
CLKIN
FS
VDD
SSEXTR
MR
PD#
GND
Rs
ModOUT
ORDERING INFORMATION
†
Ordering Code
Marking
Temperature
Package Type
Shipping
P3PSL450AG−08CR
FA
−20°C to +85°C
8− pin (2 mm x 2 mm) WDFN
(Pb−Free)
Tape & Reel
Tape & Reel
P3PSL450AHG−08CR
FC
−20°C to +85°C
8− pin (2 mm x 2 mm) WDFN
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free.
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8
P3PSL450A
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
D
A
B
L
L
L1
PIN ONE
DETAIL A
MILLIMETERS
REFERENCE
2X
E
OPTIONAL
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
CONSTRUCTIONS
0.10
C
A1
A3
b
0.20 REF
0.20
0.30
0.10
C
2X
D
2.00 BSC
EXPOSED Cu
MOLD CMPD
TOP VIEW
E
2.00 BSC
0.50 BSC
e
L
0.50
---
0.60
0.15
A3
DETAIL B
L1
0.05
C
C
DETAIL B
OPTIONAL
A
8X
CONSTRUCTION
RECOMMENDED
0.05
SOLDERING FOOTPRINT*
A1
SEATING
PLANE
C
7X
SIDE VIEW
0.78
PACKAGE
OUTLINE
DETAIL A
1
8X L
4
2.30
0.88
1
0.50
PITCH
8
5
8X
0.35
8X b
e/2
e
0.10
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
C
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
P3PSL450A/D
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