PCA9654EMTTBG [ONSEMI]
IC SPECIALTY INTERFACE CIRCUIT, Interface IC:Other;型号: | PCA9654EMTTBG |
厂家: | ONSEMI |
描述: | IC SPECIALTY INTERFACE CIRCUIT, Interface IC:Other 接口集成电路 |
文件: | 总22页 (文件大小:317K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCA9654E, PCA9654EA
8-bit I/O Expander for I2C
Bus and SMBus with
Interrupt
The PCA9654E/PCA9654EA provides 8 bits of General Purpose
2
parallel Input/Output (GPIO) expansion for I C−bus/SMBus
applications.
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MARKING
The PCA9654E/PCA9654EA consists of 8−bit Configuration
(Input or Output selection); Input, Output and Polarity Inversion
(active HIGH or active LOW operation) registers. The system master
may set the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each Input or Output is kept in the
corresponding Input or Output register. The polarity of the read
register can be inverted with the Polarity Inversion register. All
registers can be read by the system master.
DIAGRAMS
16
1
1
PCA9654E
AWLYWWG
SOIC−16
D SUFFIX
CASE 751B
The PCA9654E/PCA9654EA open−drain interrupt (INT) output is
activated when any input state differs from its corresponding input
port register state and is used to indicate to the system master that an
input state has changed. The power−on reset sets the registers to their
default values and initializes the device state machine.
16
PCA9
654E
ALYWG
G
1
TSSOP−16
DT SUFFIX
CASE 948F
2
1
1
Three hardware pins (AD0, AD1, AD2) vary the fixed I C bus
2
address and allow up to 64 devices to share the same I C−bus/SMBus.
16
The PCA9654EA has a different address map from the PCA9654E.
Features
XXMG
1
• V Operating Range: 1.65 V to 5.5 V
DD
G
WQFN16
MT SUFFIX
CASE 488AP
• SDA Sink Capability: 30 mA
• 5.5 V Tolerant I/Os
• Polarity Inversion Register
16
• Active LOW Interrupt Output
• Low Standby Current
1
1
XXXX
XXXX
ALYWG
G
1
QFN16 3x3
MN SUFFIX
CASE 485G
• Noise Filter on SCL/SDA Inputs
• No Glitch on Power−up
• Internal Power−on Reset
16
• 64 Programmable Slave Addresses Using 3 Address Pins
• 8 I/O Pins which Default to 8 Inputs
XXXXXX
XXXXXX
ALYWG
G
1
2
QFN16 4x4
MN SUFFIX
CASE 485AP
• I C SCL Clock Frequencies Supported:
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
XXXX = Specific Device Code
A
M
= Assembly Location
• ESD Performance: 4000 V Human Body Model,
400 V Machine Model
= Date Code / Assembly Location
WL, L = Wafer Lot
= Year
WW, W = Work Week
Y
• These are Pb−Free Devices
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May, 2014 − Rev. 1
PCA9654E/D
PCA9654E, PCA9654EA
BLOCK DIAGRAM
Remark: All I/Os are set to inputs at reset.
Figure 1. Block Diagram
data from
output port
shift register
register data
configuration
register
V
DD
data from
shift register
Q1
D
Q
100 kW
FF
write
configuration
pulse
D
Q
CK
Q
FF
I/O pin
Q2
write pulse
CK
V
input port
register
SS
output port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
polarity
inversion
register data
D
Q
FF
write polarity
pulse
CK
At power−on reset, all registers return to default values.
Figure 2. Simplified Schematic of I/Os
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2
PCA9654E, PCA9654EA
PIN ASSIGNMENT
terminal 1
index area
1
AD2
IO0
IO1
IO2
12 SCL
11
2
3
4
INT
10 IO7
PCA9654E
PCA9654EA
16 V
1
2
3
4
5
6
7
8
AD0
AD1
AD2
IO0
IO1
IO2
IO3
DD
15
14
13
12
11
SDA
SCL
INT
IO7
IO6
9
IO6
PCA9654E
PCA9654EA
10 IO5
9
IO4
V
SS
Transparent top view
Figure 4. WQFN16 / QFN16
Figure 3. SOIC16 / TSSOP16
Table 1. PIN DESCRIPTIONS
Pin
SOIC16, TSSOP16
QFN16, WQFN16
Symbol
AD0
AD1
AD2
IO0
Description
1
2
15
16
1
Address Input 0
Address Input 1
Address Input 2
I/O 0
3
4
2
IO1
5
3
I/O 1
IO2
6
4
I/O 2
IO3
7
5
I/O 3
V
8
6
Supply Ground
I/O 4
SS
IO4
IO5
IO6
IO7
INT
SCL
SDA
9
7
10
11
12
13
14
15
16
8
I/O 5
9
I/O 6
10
11
12
13
14
I/O 7
Interrupt Output (active−LOW)
Serial Clock Line
Serial Data Line
Supply Voltage
V
DD
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3
PCA9654E, PCA9654EA
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
$20
Unit
V
V
DD
DC Supply Voltage
V
Input / Output Pin Voltage
Input Current
V
I/O
I
mA
mA
mA
mA
mW
mW
°C
I
I
O
Output Current
$50
I
DC Supply Current
$100
DD
I
DC Ground Current
Total Power Dissipation
Power Dissipation per Output
Storage Temperature Range
$200
GND
P
400
TOT
OUT
STG
P
T
100
−65 to +150
260
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
°C
L
T
150
°C
J
q
SOIC−16 (Note 1)
TSSOP−16
82
124
79
°C/W
JA
WQFN16
3 x 3 QFN16
4 x 4 QFN16
80
80
P
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
190
Level 1
mW
D
MSL
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 4000
> 400
N/A
V
I
Latchup Performance Above V and Below GND at 125°C (Note 5)
$300
mA
LATCHUP
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
5.5
Unit
V
V
DD
Positive DC Supply Voltage
V
I/O
Switch Input / Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
5.5
V
T
A
−55
0
+125
5
°C
Dt / DV
nS/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
PCA9654E, PCA9654EA
Table 4. DC ELECTRICAL CHARACTERISTICS V = 1.65 V to 5.5 V, unless otherwise specified.
DD
T
= −555C to +1255C
A
Min
Typ
Max
Symbol
Parameter
Conditions
Unit
SUPPLIES
I
Supply Current
Operating mode; no load;
mA
DD
V = V or 0 V; f
= 1 MHz
= 100 kHz
250
104
500
175
I
DD
SCL
SCL
V = V or 0 V; f
I
DD
I
Standby Current
Standby mode; no load;
mA
STB
V = 0 V; f
= 0 Hz; I/O = inputs
= 0 Hz; I/O = inputs
DD SCL
550
0.25
700
1
I
SCL
V = V ; f
I
V
POR
Power−On Reset Voltage (Note 6)
1.5
V
INPUT SCL; Input / Output SDA
V
High−Level Input Voltage
Low−Level Input Voltage
Low−Level Output Current
0.7 x V
V
V
IH
DD
V
I
0.3 x V
IL
DD
mA
V
V
= 0.4 V; V < 2.3 V
10
20
OL
OL
DD
= 0.4 V; V w 2.3 V
OL
DD
I
Leakage Current
Input Capacitance
V = V or GND
$1
mA
L
I
DD
C
V = GND
I
6
pF
I
I/Os
V
High−Level Input Voltage
Low−Level Input Voltage
2.3 V ≤ V ≤ 5.5 V
2.0
0.7 x V
V
V
IH
CC
1.65 V ≤ V ≤ 2.3 V
CC
DD
V
2.3 V ≤ V ≤ 5.5 V
0.8
0.3 x V
IL
CC
1.65 V ≤ V ≤ 2.3 V
CC
DD
I
OL
Low−Level Output Current
(Note 7)
V
OL
V
OL
V
OL
V
OL
= 0.5 V; V = 1.65 V
8
13
22
28
37
mA
DD
= 0.5 V; V = 2.3 V
12
17
25
DD
= 0.5 V; V = 3.0 V
DD
= 0.5 V; V = 4.5 V
DD
I
Total Low−Level Output Current
(Note 7)
V
= 0.5 V; V = 4.5 V
200
mA
V
OL(tot)
OL
DD
V
OH
High−Level Output Voltage
I
I
I
I
I
I
I
I
= −3 mA; V = 1.65 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
OH
OH
OH
OH
OH
OH
OH
OH
DD
= −4 mA; V = 1.65 V
DD
= −8 mA; V = 2.3 V
DD
= −10 mA; V = 2.3 V
DD
= −8 mA; V = 3.0 V
DD
= −10 mA; V = 3.0 V
DD
= −8 mA; V = 4.5 V
DD
= −10 mA; V = 4.5 V
DD
I
Input Leakage Current
Input Leakage Current
V
V
= 5.5 V; V = V
DD
1
mA
mA
pF
LH
DD
I
I
= 5.5 V; V = GND
−100
5
LL
DD
I
C
Input / Output Capacitance
(Note 8)
3.7
2.1
I/O
INTERRUPT (INT)
I
OL
Low−Level Output Current
Output Capacitance
V
OL
= 0.4 V
6
mA
pF
C
5
O
INPUTS AD0, AD1, AD2
High−Level Input Voltage
V
IH
2.3 V ≤ V ≤ 5.5 V
2.0
0.7 x V
V
V
CC
1.65 V ≤ V ≤ 2.3 V
CC
DD
V
IL
Low−Level Input Voltage
2.3 V ≤ V ≤ 5.5 V
0.8
0.3 x V
CC
1.65 V ≤ V ≤ 2.3 V
CC
DD
I
Leakage Current
Input Capacitance
V = V or GND
$1
mA
L
I
DD
C
2.4
5
pF
I
2
6. The power−on reset circuit resets the I C bus logic with V < V
and set all I/Os to logic 1 upon power−up. Thereafter, V must be lower
DD
DD
POR
than 0.2 V to reset the part.
7. Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal bussing limits.
8. The value is not tested, but verified on sampling basis.
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5
PCA9654E, PCA9654EA
Table 5. AC ELECTRICAL CHARACTERISTICS V = 1.65 V to 5.5 V; T = −55°C to +125°C, unless otherwise specified.
DD
A
Standard
Mode
Fast Mode
Fast Mode +
Min
Max
Min
0
Max
Min
0
Max
Symbol
Parameter
SCL Clock Frequency
Unit
MHz
ms
f
0
0.1
0.4
1.0
SCL
BUF
t
Bus−Free Time between a STOP and START
Condition
4.7
1.3
0.5
t
Hold Time (Repeated) START Condition
4.0
4.7
0.6
0.6
0.26
0.26
ms
ms
HD:STA
t
Setup Time for a Repeated START Condition
SU:STA
t
Setup Time for STOP Condition
4.0
0.6
0.26
ms
SU:STO
t
Data Hold Time
0
0
0
ns
ms
ns
ns
ms
ms
ns
HD:DAT
t
Data Valid Acknowledge Time (Note 9)
Data Valid Time (Note 10)
Data Setup Time
0.3
300
250
4.7
4.0
3.45
0.1
50
0.9
0.05
50
0.45
450
VD:ACK
t
t
VD:DAT
100
1.3
0.6
50
SU:DAT
t
LOW Period of SCL
0.5
0.26
LOW
t
HIGH Period of SCL
HIGH
t
f
Fall Time of SDA and SCL (Notes 12 and 13)
300
1000
50
20 + 0.1C
(Note 11)
300
300
50
120
120
50
b
t
r
Rise Time of SDA and SCL
20 + 0.1C
(Note 11)
ns
ns
b
t
SP
Pulse Width of Spikes Suppressed by Input Filter
(Note 14)
PORT TIMING: C v 100 pF (See Figures 7 and 10)
L
t
Data Output Valid Time
Data Input Setup Time
Data Input Hold Time
350
350
350
ns
ns
ms
V(Q)
t
100
1
100
1
100
1
SU(D)
t
H(D)
INTERRUPT TIMING: C v 100 pF (See Figure 10)
V(INT_N)
L
t
Data Valid Time
4
4
4
4
4
4
ms
ms
t
Reset Delay Time
RST(INT_N)
9. t
10.t
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
= minimum time for SDA data out to be valid following SCL LOW.
VD:ACK
VD:DAT
11. C = total capacitance of one bus line in pF.
b
12.A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V of the SCL signal) in order to bridge
IL
the undefined region SCL’s falling edge.
13.The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t is specified at 250 ns.
f
f
This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified t .
f
14.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
PCA9654E, PCA9654EA
slave address
A3
Device Address
Following a START condition, the bus master must send
the address of the slave it is accessing and the operation it
wants to perform (read or write). The address of the
PCA9654E/PCA9654EA is shown in Figure 5. Slave
address pins AD2, AD1, and AD0 choose 1 of 64 slave
addresses. To conserve power, no internal pull−up resistors
are incorporated on AD2, AD1, and AD0. Address values
can be found on Table 6 “PCA9654E Address Map” and
Table 7 “PCA9654EA Address Map”.
A6
A5
A4
A2
A1
A0
R/W
programmable
Figure 5. PCA9654E / PCA9654EA Device Address
A logic 1 on the last bit of the first byte selects a read operation while a logic 0 selects a write operation.
Table 6. PCA9654E ADDRESS MAP
Address Input
AD1
Slave Address
A3
AD2
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
AD0
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
HEX
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
SCL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
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7
PCA9654E, PCA9654EA
Table 6. PCA9654E ADDRESS MAP
Address Input
Slave Address
AD2
VDD
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
AD1
VDD
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
AD0
SDA
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
VDD
GND
VDD
GND
VDD
GND
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
A6
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
5Eh
A0h
A2h
A4h
A6h
A8h
AAh
ACh
AEh
B0h
B2h
B4h
B6h
B8h
BAh
BCh
BEh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
CEh
E0h
E2h
E4h
E6h
E8h
EAh
ECh
EEh
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8
PCA9654E, PCA9654EA
Table 7. PCA9654EA ADDRESS MAP
Address Input
Slave Address
AD2
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
AD1
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
AD0
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SCL
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
HEX
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
9Ch
9Eh
D0h
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9
PCA9654E, PCA9654EA
Table 7. PCA9654EA ADDRESS MAP
Address Input
Slave Address
AD2
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
AD1
SCL
SDA
SDA
SCL
SCL
SDA
SDA
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
AD0
SDA
SCL
SDA
SCL
SDA
SCL
SDA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
A2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
D2h
D4h
D6h
D8h
DAh
DCh
DEh
F0h
F2h
F4h
F6h
− (Note 15)
FAh
FCh
FEh
− (Note 15)
02h
04h
06h
08h
0Ah
0Ch
0Eh
15.The PCA9654EA does not acknowledge this AD2, AD1 and AD0 configuration.
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10
PCA9654E, PCA9654EA
REGISTERS
Command Byte
Table 8. COMMAND BYTE
COMMAND
PROTOCOL
REGISTER
0
1
2
3
Read byte
Input Port
Read / Write byte
Read / Write byte
Read / Write byte
Output Port
Polarity Inversion
Configuration
The command byte is the first byte to follow the address
byte during a write transmission. It is used as a pointer to
determine which of the following registers will be written or
read.
Register 0 − Input Port Register
This register is a read−only port. It reflects the incoming
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Register 3. Writes to this
register have no effect.
The default ‘X’ is determined by the externally applied
logic level, normally ‘1’ when no external signal externally
applied because of the internal pull−up resistors.
Table 9. INPUT PORT REGISTER
Bit
7
I7
R
X
6
I6
R
X
5
I5
R
X
4
I4
R
X
3
I3
R
X
2
I2
R
X
1
I1
R
X
0
I0
R
X
Symbol
Access
Default
Register 1 − Output Port Register
This register reflects the outgoing logic levels of the pins
defined as outputs by Register 3. Bit values in this register
have no effect on pins defined as inputs. Reads from this
register return the value that is in the flip−flop controlling the
output selection, not the actual pin value.
Table 10. OUTPUT PORT REGISTER
Bit
7
O7
R/W
1
6
O6
R/W
1
5
O5
R/W
1
4
O4
R/W
1
3
O3
R/W
1
2
O2
R/W
1
1
O1
R/W
1
0
O0
R/W
1
Symbol
Access
Default
Register 2 − Polarity Inversion Register
This register allows the user to invert the polarity of the
Input Port register data. If a bit in this register is set (written
with ‘1’), the corresponding Input Port data is inverted. If a
bit in this register is cleared (written with a ‘0’), the Input
Port data polarity is retained.
Table 11. POLARITY INVERSION REGISTER
Bit
7
N7
R/W
0
6
N6
R/W
0
5
N5
R/W
0
4
N4
R/W
0
3
N3
R/W
0
2
N2
R/W
0
1
N1
R/W
0
0
N0
R/W
0
Symbol
Access
Default
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11
PCA9654E, PCA9654EA
Register 3 − Configuration Register
This register configures the directions of the I/O pins. If
a bit in this register is set, the corresponding port pin is
enabled as an input with high−impedance output driver. If a
bit in this register is cleared, the corresponding port pin is
enabled as an output. At reset, the I/Os are configured as
inputs with a weak pull−up to V
.
DD
Table 12. CONFIGURATION REGISTER
Bit
7
C7
R/W
1
6
C6
R/W
1
5
C5
R/W
1
4
C4
R/W
1
3
C3
R/W
1
2
C2
R/W
1
1
C1
R/W
1
0
C0
R/W
1
Symbol
Access
Default
Power−on Reset
I/O Port (Figure 2)
When power is applied to V , an internal Power−On
Reset (POR) holds the PCA9654E/PCA9654EA in a reset
When an I/O is configured as an input, FETs Q1 and Q2
are off, creating a high−impedance input with a weak
DD
condition until V has reached V
. At that point, the
POR
pull−up (100 kW typ.) to V . The input voltage may be
DD
DD
reset condition is released and the PCA9654E/ PCA9654EA
registers and state machine will initialize to their default
raised above V to a maximum of 5.5 V.
DD
If the I/O is configured as an output, then either Q1 or Q2
is enabled, depending on the state of the Output Port register.
Care should be exercised if an external voltage is applied to
an I/O configured as an output because of the
low−impedance paths that exist between the pin and either
states. Thereafter, V must be lowered below 0.2 V to reset
DD
the device.
For a power reset cycle, V must be lowered below
DD
0.2 V and then restored to the operating voltage. Please refer
to application note AN# TBD for recommended power−on
sequence and power−reset cycle profile.
V
DD
or V .
SS
Interrupt Output
The open−drain interrupt output is activated when one of
the port pins changes state and the pin is configured as an
input. The interrupt is deactivated when the input returns to
its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
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12
PCA9654E, PCA9654EA
BUS TRANSACTIONS
Data is transmitted to the PCA9654E/PCA9654EA
Figure 9. These devices do not implement an
auto−increment function, so once a command byte has been
sent, the register which was addressed will continue to be
accessed by reads until a new command byte has been sent.
registers using the Write mode as shown in Figure 6 and
Figure 7. Data is read from the PCA9654E/PCA9654EA
registers using the Read mode as shown in Figure 8 and
Figure 6. Write to Output Port Registers
Figure 7. Write to Configuration or Polarity Inversion Register
Figure 8. Read from Register
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13
PCA9654E, PCA9654EA
Figure 9. Read Input Port Register
APPLICATION INFORMATION
Figure 10. Typical Application
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14
PCA9654E, PCA9654EA
Characteristics of the I2C−Bus
Bit Transfer
2
The I C−bus is for 2−way, 2−line communication between
different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull−up resistor when
connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 11).
SDA
SCL
data line
stable;
change
of data
data valid
allowed
Figure 11. Bit Transfer
START and STOP Conditions
Both data and clock lines remain HIGH when the bus is
not busy. A HIGH−to−LOW transition of the data line while
the clock is HIGH is defined as the START condition (S). A
LOW−to−HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P) (see Figure 12).
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
Figure 12. Definition of START and STOP Conditions
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 13).
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
2
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C−BUS
TRANSMITTER/
RECEIVER
MULTIPLEXER
SLAVE
Figure 13. System Configuration
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15
PCA9654E, PCA9654EA
Acknowledge
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge
related clock pulse; set−up time and hold time must be taken
into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
data output
by transmitter
not acknowledge
acknowledge
data output
by receiver
SCL from master
1
2
8
9
S
clock pulse for
START
acknowledgement
condition
Figure 14. Acknowledgement of the I2C Bus
TIMING AND TEST SETUP
SDA
SCL
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
Figure 15. Definition of Timing on the I2C Bus
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16
PCA9654E, PCA9654EA
V
DD
open
GND
V
R
500 W
DD
L
V
I
V
O
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
R = load resistor.
L
C = load capacitance includes jig and probe capacitance.
L
R = termination resistance should be equal to the output impedance of Z of the pulse generators.
T
o
Figure 16. Test Circuitry for Switching Times
R
L
2V
DD
S1
from output under test
open
GND
500 W
C
50 pF
R
L
500 W
L
Figure 17. Load Circuit
Package
ORDERING INFORMATION
Device
†
Shipping
PCA9654EDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
2000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
2000 / Tape & Reel
PCA9654EDTR2G
TSSOP−16
(Pb−Free)
PCA9654EMTTBG
(In Development)
WQFN16
(Pb−Free)
PCA9654E3MNTWG
(In Development)
QFN16 (3x3)
(Pb−Free)
PCA9654E4MNTWG
(In Development)
QFN16 (4x4)
(Pb−Free)
PCA9654EADR2G
(In Development)
SOIC−16
(Pb−Free)
PCA9654EADTR2G
(In Development)
TSSOP−16
(Pb−Free)
PCA9654EAMTTBG
(In Development)
WQFN16
(Pb−Free)
PCA9654EA3MNTWG
(In Development)
QFN16 (3x3)
(Pb−Free)
PCA9654EA4MNTWG
(In Development)
QFN16 (4x4)
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
PCA9654E, PCA9654EA
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
0.25 (0.010)
T B
A
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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18
PCA9654E, PCA9654EA
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
N
−V−
A
B
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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19
PCA9654E, PCA9654EA
PACKAGE DIMENSIONS
WQFN16, 1.8x2.6, 0.4P
CASE 488AP
ISSUE B
L
L
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
L1
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
PIN 1 REFERENCE
E
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
MILLIMETERS
A3
EXPOSED Cu
MOLD CMPD
DIM MIN
MAX
0.80
0.15
0.15
C
2X
A
A1
A3
b
0.70
0.00
0.050
0.20 REF
C
2X
0.15
0.25
B
A1
D
1.80 BSC
2.60 BSC
0.40 BSC
E
DETAIL B
e
A
ALTERNATE
DETAIL B
L
0.30
0.00
0.40
0.50
0.15
0.60
0.10
0.08
C
CONSTRUCTIONS
L1
L2
C
SEATING
PLANE
A1
DETAIL A
C
A3
MOUNTING FOOTPRINT
5
8
0.562
0.0221
15 X L
0.400
0.0157
4
1
9
0.225
1
e
0.0089
12
2.900
0.1142
16
L2
16 X
0.10 C A B
0.05 C
0.463
0.0182
b
NOTE 3
1.200
0.0472
2.100
0.0827
mm
inches
ǒ
Ǔ
SCALE 20:1
http://onsemi.com
20
PCA9654E, PCA9654EA
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
NOM MAX
A
0.90
0.03
1.00
0.05
2X
A3
0.10
C
EXPOSED Cu
MOLD CMPD
A3
b
D
0.20 REF
0.24
3.00 BSC
1.75
0.18
0.30
1.85
1.85
2X
0.10
C
TOP VIEW
D2 1.65
E
3.00 BSC
1.75
0.50 BSC
0.18 TYP
0.40
DETAIL B
A1
(A3)
E2 1.65
e
K
L
0.05
0.05
C
DETAIL B
ALTERNATE
A
C
0.30
0.50
0.15
CONSTRUCTIONS
L1 0.00
0.08
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A
B
16X
0.58
DETAIL A
D2
PACKAGE
OUTLINE
16X
L
8
4
1
9
1
2X
1.84
2X
3.30
E2
16X
K
16X
0.30
16
16X b
e
0.10 C A
B
0.50
e/2
BOTTOM VIEW
0.05
C
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
21
PCA9654E, PCA9654EA
PACKAGE DIMENSIONS
QFN16 4x4, 0.65P
CASE 485AP
ISSUE A
NOTES:
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
REFERENCE
DETAIL A
OPTIONAL LEAD
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
A3
EXPOSED Cu
MOLD CMPD
2X
0.15
C
TOP VIEW
0.25
0.35
2X
0.15
C
D
4.00 BSC
D2
E
E2
e
K
L
2.00
4.00 BSC
2.00
0.65 BSC
0.20
0.45
−−−
2.20
A
L
(A3)
A1
DETAIL B
2.20
0.10
C
DETAIL B
OPTIONAL LEAD
CONSTRUCTIONS
−−−
0.65
0.15
16X
L1
0.08
C
SIDE VIEW
D2
A1
NOTE 4
SEATING
PLANE
C
DETAIL A
MOUNTING FOOTPRINT*
16X
4.30
2.25
5
8
4
9
PKG
OUTLINE
E2
1
1
12
16X b
16
13
16X
K
e
0.10 C A
B
0.05
C
NOTE 3
0.65
BOTTOM VIEW
4.30
2.25
PITCH
16X
16X
0.35
0.78
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
PCA9654E/D
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