PCF8896W [ONSEMI]
N 沟道，PowerTrench® MOSFET，30V，15A，6.0mΩ;
| 型号： | PCF8896W |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，30V，15A，6.0mΩ |
| 文件： | 总13页 (文件大小：801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FDS8896
N-Channel PowerTrench® MOSFET
30V, 15A, 6.0mΩ
Features
General Description
rDS(on) = 6.0mΩ, VGS = 10V, ID = 15A
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
rDS(on) = 7.3mΩ, VGS = 4.5V, ID = 14A
High performance trench technology for extremely low
rDS(on)
rDS(on) and fast switching speed.
Applications
Low gate charge
DC/DC converters
High power and current handling capability
RoHS Compliant
Branding Dash
5
6
7
8
4
3
2
1
5
1
2
3
4
SO-8
©2007 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
1
Publication Order Number:
FDS8896/D
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
30
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±20
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)
Continuous (TA = 25oC, VGS = 4.5V, RθJA = 50oC/W)
Pulsed
15
14
A
A
ID
110
A
EAS
Single Pulse Avalanche Energy (Note 1)
196
mJ
Power dissipation
Derate above 25oC
2.5
W
PD
20
mW/oC
oC
TJ, TSTG
Operating and Storage Temperature
-55 to 150
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance, Junction to Case (Note 2)
25
50
oC/W
oC/W
oC/W
Thermal Resistance, Junction to Ambient (Note 2a)
Thermal Resistance, Junction to Ambient (Note 2b)
125
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
12mm
Quantity
2500 units
FDS8896
FDS8896
SO-8
330mm
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
30
-
-
-
-
-
-
V
V
DS = 24V
1
IDSS
µA
VGS = 0V
TJ = 150oC
-
250
±100
IGSS
VGS = ±20V
-
nA
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
D = 15A, VGS = 10V
1.2
-
2.5
6.0
7.3
V
I
-
-
4.9
5.8
ID = 14A, VGS = 4.5V
rDS(on)
Drain to Source On Resistance
mΩ
ID = 15A, VGS = 10V,
TJ = 150oC
-
7.8
10.1
Dynamic Characteristics
CISS
COSS
CRSS
RG
Input Capacitance
-
2525
490
300
2.4
50
-
-
pF
pF
pF
Ω
VDS = 15V, VGS = 0V,
f = 1MHz
Output Capacitance
-
Reverse Transfer Capacitance
Gate Resistance
-
-
VGS = 0.5V, f = 1MHz
VGS = 0V to 10V
0.6
4.2
67
36
3.2
-
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
VDD = 15V
D = 15A
Ig = 1.0mA
VGS = 0V to 5V
VGS = 0V to 1V
28
I
2.5
7.0
4.5
11
Qgs2
Qgd
-
-
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2
Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
68
ns
ns
ns
ns
ns
ns
8
-
37
60
24
-
-
VDD = 15V, ID = 14A
VGS = 10V, RGS = 6.2Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
126
Drain-Source Diode Characteristics
I
SD = 15A
-
-
-
-
-
-
-
-
1.25
1.0
29
V
V
VSD
Source to Drain Diode Voltage
ISD = 2.1A
trr
Reverse Recovery Time
ISD = 15A, dISD/dt = 100A/µs
ISD = 15A, dISD/dt = 100A/µs
ns
nC
QRR
Reverse Recovered Charge
15
Notes:
1: Starting T = 25°C, L = 1mH, I = 19.8A, V = 30V, V = 10V.
J
AS
DD
GS
2:
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
θJA
drain pins. R
is guaranteed by design while R
2
is determined by the user’s board design.
θJA
θJC
a) 50°C/W when mounted on a 1in pad of 2 oz copper.
b) 125°C/W when mounted on a minimum pad.
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3
Typical Characteristics TJ = 25°C unless otherwise noted
20
15
10
5
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 10V
GS
V
= 4.5V
GS
o
R
=50 C/W
θJA
0
0
25
50
75
100
125
150
25
50
T
75
100
125
150
o
o
, AMBIENT TEMPERATURE ( C)
T
, AMBIENT TEMPERATURE ( C)
A
A
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
R
θJA = 125oC/W
0.001
0.0005
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
100
10
1
0.5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
Figure 4. Single Pulse Maximum Power Dissipation
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4
Typical Characteristics TJ = 25°C unless otherwise noted
100
50
40
30
20
10
0
If R = 0
= (L)(I )/(1.3*RATED BV
PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX
t
AV
- V
)
AS
DSS
DD
If R ≠ 0
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DD
AV
AS
DSS
VDS = 5V
o
STARTING T = 25 C
J
10
TJ = 25oC
TJ = 150oC
o
STARTING T = 150 C
J
TJ = -55oC
1
1.5
2.0
2.5
3.0
3.5
0.1
1
10
100
VGS, GATE TO SOURCE VOLTAGE (V)
t
, TIME IN AVALANCHE (ms)
AV
NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching
Capability
Figure 6. Transfer Characteristics
50
14
12
10
8
V
= 5V
V
= 10V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
GS
I
= 15A
D
V
= 4V
GS
40
30
20
10
0
V
= 3V
GS
o
T
= 25 C
A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
6
V
= 2.5V
GS
4
0
0.1
0.2
0.3
0.4
0.5
2
4
V , GATE TO SOURCE VOLTAGE (V)
GS
6
8
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.2
1.6
PULSE DURATION = 80µs
V
= V , I = 250µA
GS
DS
D
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
0.6
1.0
0.8
0.6
V
= 10V, I = 15A
D
GS
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
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5
Typical Characteristics TJ = 25°C unless otherwise noted
1.10
1.05
1.00
0.95
0.90
5000
I
= 250µA
C
= C + C
GS GD
D
ISS
C
≅ C + C
DS GD
OSS
1000
C
= C
GD
RSS
V
= 0V, f = 1MHz
GS
100
-80
-40
0
40
80
120
160
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
o
T , JUNCTION TEMPERATURE ( C)
V
J
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
10
200
100
V
= 15V
DD
100us
8
6
4
2
0
10
1
1ms
10ms
THIS AREA IS
LIMITED BY r
100ms
1s
DS(on)
SINGLE PULSE
J = MAX RATED
RθJA = 125oC/W
T
0.1
WAVEFORMS IN
10s
DC
DESCENDING ORDER:
I
I
= 15A
= 1A
D
T
A = 25oC
D
0.01
0.01
0.1
1
10
100
0
10
20
30
40
50
VDS, DRAIN to SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 13. Gate Charge Waveforms for Constant
Gate Currents
Figure 14. Forward Bias Safe Operating Area
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6
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
V
GS
DS
L
V
= 10V
GS
Q
g(5)
V
GS
+
-
Q
gs2
V
= 5V
GS
V
DD
DUT
V
= 1V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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7
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
26
R
= 64 +
-------------------------------
(EQ. 2)
θJA
0.23 + Area
(T
– T )
A
JM
(EQ. 1)
P
= ------------------------------
DM
RθJA
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal imped-
ance. Each trace represents a copper pad area in square
inches corresponding to the descending list in the graph.
Spice and SABER thermal models are provided for each of
the listed pad areas.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 64 + 26/(0.23+Area)
θJA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
ON Semiconductor provides thermal information to assist
the design-er’s preliminary application evaluation. Figure
21 defines the RθJA for the device as a function of the top
copper (compo-nent side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary in-formation for calculation of the steady
state junction temper-ature or power dissipation. Pulse
applications can be evaluated using the ON Semiconductor
device Spice thermal model or manually utilizing the
normalized maximum transient
100
50
0.001
0.01
0.1
1
2
10
AREA, TOP COPPER AREA (in )
Figure 21. Thermal Resistance vs Mounting
Pad Area
150
COPPER BOARD AREA - DESCENDING ORDER
2
0.04 in
2
0.28 in
0.52 in
0.76 in
1.00 in
120
90
60
30
0
2
2
2
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 22. Thermal Impedance vs Mounting Pad Area
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8
PSPICE Electrical Model
.SUBCKT FDS8896 2 1 3 ;
Ca 12 8 1.8e-9
rev February 2004
Cb 15 14 1.8e-9
Cin 6 8 2.2e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
Ebreak 11 7 17 18 33.1
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
-
+
50
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
MWEAK
ESG
It 8 17 1
EVTHRES
+
16
21
+
-
19
8
Lgate 1 9 1.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1e-9
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
RLgate 1 9 15
RLdrain 2 5 10
RLsource 3 7 10
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.52e-3
Rgate 9 20 2.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=8.8e-10 M=0.57 TT=1e-12 XTI=2.2)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9e-10 IS=1e-30 N=10 M=0.39)
.MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.4)
.MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.63 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=24 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-1e-6)
.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.3e-3 TC2=-7e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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9
SABER Electrical Model
REV February 2004
template FDS8896 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-12,xti=2.2)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9e-10,isl=10e-30,nl=10,m=0.39)
m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.63,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 1.8e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
c.cb n15 n14 = 1.8e-9
c.cin n6 n8 = 2.2e-9
RSLC2
ISCL
DBREAK
11
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
spe.ebreak n11 n7 n17 n18 = 33.1
MWEAK
LGATE
EVTEMP
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
RBREAK
l.lgate n1 n9 = 1.5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1e-9
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
res.rlgate n1 n9 = 15
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 10
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-1e-6
res.rdrain n50 n16 = 2.52e-3, tc1=1e-4,tc2=8e-6
res.rgate n9 n20 = 2.4
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.3e-3,tc2=-7e-6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
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10
SPICE Thermal Model
JUNCTION
th
REV February 2004
FDS8896T
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
6
5
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
4
3
2
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
tl
CASE
TABLE 1. THERMAL MODELS
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in2
1.2e-1
0.5
0.28 in2
1.5e-1
1.0
0.52 in2
2.0e-1
1.0
0.76 in2
2.0e-1
1.0
1.0 in2
2.0e-1
1.0
3.0
12
1.3
2.8
3.0
3.0
26
20
15
13
39
24
21
19
18
55
38.7
31.3
29.7
25
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